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| 3-Axis, 2 g/4 g/8 g/16 g Ultralow Power Digital Accelerometer ADXL346 FEATURES Ultralow power: as low as 23 A in measurement mode and 0.2 A in standby mode at VS = 2.6 V (typical) Power consumption scales automatically with bandwidth User-selectable resolution Fixed 10-bit resolution Full resolution, where resolution increases with g range, up to 13-bit resolution at 16 g (maintaining 4 mg/LSB scale factor in all g ranges) Patent pending, embedded memory management system with FIFO technology minimizes host processor load Single-tap/double-tap detection Activity/inactivity monitoring Free-fall detection Concurrent four- and six-position orientation detection Supply and I/O voltage range: 1.7 V to 2.75 V SPI (3- and 4-wire) and I2C digital interfaces Flexible interrupt modes mappable to either interrupt pin Measurement ranges selectable via serial command Bandwidth selectable via serial command Wide temperature range (-40C to +85C) 10,000 g shock survival Pb free/RoHS compliant Small and thin: 3 mm x 3 mm x 0.95 mm LGA package GENERAL DESCRIPTION The ADXL346 is a small, thin, ultralow power, 3-axis accelerometer with high resolution (13-bit) measurement at up to 16 g. Digital output data is formatted as 16-bit twos complement and is accessible through either an SPI (3- or 4-wire) or I2C(R) digital interface. The ADXL346 is well suited for mobile device applications. It measures the static acceleration of gravity in tilt-sensing applications, as well as dynamic acceleration resulting from motion or shock. Its high resolution (4 mg/LSB) enables measurement of inclination changes of less than 1.0. Several special sensing functions are provided. Activity and inactivity sensing detect the presence or lack of motion by comparing the acceleration on any axis with user-set thresholds. Tap sensing detects single and double taps in any direction. Freefall sensing detects if the device is falling. Orientation detection is capable of concurrent four- and six-position sensing and a user-selectable interrupt on orientation change for 2D or 3D applications. These functions can be mapped individually to either of two interrupt output pins. An integrated, patent pending memory management system with 32-level first in, first out (FIFO) buffer can be used to store data to minimize host processor activity and lower overall system power consumption. Low power modes enable intelligent motion-based power management with threshold sensing and active acceleration measurement at extremely low power dissipation. The ADXL346 is supplied in a small, thin, 3 mm x 3 mm x 0.95 mm, 16-lead, plastic package. APPLICATIONS Handsets Medical instrumentation Gaming and pointing devices Industrial instrumentation Personal navigation devices Hard disk drive (HDD) protection FUNCTIONAL BLOCK DIAGRAM VS VDD I/O ADXL346 POWER MANAGEMENT SENSE ELECTRONICS 3-AXIS SENSOR ADC DIGITAL FILTER CONTROL AND INTERRUPT LOGIC INT1 INT2 32-LEVEL FIFO SDA/SDI/SDIO SERIAL I/O SDO/ALT ADDRESS SCL/SCLK 08167-001 GND CS Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved. ADXL346 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Package Information .................................................................... 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 12 Power Sequencing ...................................................................... 12 Power Savings ............................................................................. 13 Serial Communications ................................................................. 14 SPI ................................................................................................. 14 I2C ................................................................................................. 17 Interrupts ..................................................................................... 19 FIFO ............................................................................................. 20 Self-Test ........................................................................................ 21 Register Map.................................................................................... 22 Register Definitions ................................................................... 23 Applications Information .............................................................. 29 Power Supply Decoupling ......................................................... 29 Mechanical Considerations for Mounting .............................. 29 Tap Detection .............................................................................. 29 Improved Tap Detection............................................................ 30 Tap Sign ....................................................................................... 30 Threshold .................................................................................... 31 Link Mode ................................................................................... 31 Sleep Mode vs. Low Power Mode............................................. 31 Offset Calibration ....................................................................... 31 Using Self-Test ............................................................................ 32 Orientation Sensing ................................................................... 32 Data Formatting of Upper Data Rates ..................................... 34 Noise Performance ..................................................................... 35 Operation at Voltages Other Than 2.6 V ................................ 35 Offset Performance at Lowest Data Rates ............................... 36 Axes of Acceleration Sensitivity ............................................... 37 Layout and Design Recommendations ................................... 38 Outline Dimensions ....................................................................... 39 Ordering Guide .......................................................................... 39 REVISION HISTORY 5/10--Revision 0: Initial Version Rev. 0 | Page 2 of 40 ADXL346 SPECIFICATIONS TA = 25C, VS = 2.6 V, VDD I/O = 1.8 V, acceleration = 0 g, CS = 10 F tantalum, CI/O = 0.1 F, ODR = 800 Hz, unless otherwise noted. Table 1. Specifications Parameter SENSOR INPUT Measurement Range Nonlinearity Inter-Axis Alignment Error Cross-Axis Sensitivity 3 OUTPUT RESOLUTION All g Ranges 2 g Range 4 g Range 8 g Range 16 g Range SENSITIVITY Sensitivity at XOUT, YOUT, ZOUT Test Conditions Each axis User selectable Percentage of full scale Min 1 Typ 2 2, 4, 8, 16 0.5 0.1 1 10 10 11 12 13 230 230 115 57 29 3.5 3.5 7.1 14.1 28.6 256 256 128 64 32 1.0 3.9 3.9 7.8 15.6 31.2 0.02 0 35 0.7 1.3 1.1 282 282 141 71 35 4.3 4.3 8.7 17.5 34.5 Max1 Unit g % Degrees % Bits Bits Bits Bits Bits LSB/g LSB/g LSB/g LSB/g LSB/g % mg/LSB mg/LSB mg/LSB mg/LSB mg/LSB %/C mg mg mg/C mg/C LSB rms Sensitivity Deviation from Ideal Scale Factor at XOUT, YOUT, ZOUT Each axis 10-bit resolution Full resolution Full resolution Full resolution Full resolution Each axis All g ranges, full resolution 2 g, 10-bit resolution 4 g, 10-bit resolution 8 g, 10-bit resolution 16 g, 10-bit resolution All g ranges All g ranges, full resolution 2 g, 10-bit resolution 4 g, 10-bit resolution 8 g, 10-bit resolution 16 g, 10-bit resolution Each axis Sensitivity Change Due to Temperature 0 g OFFSET 0 g Output for XOUT, YOUT, ZOUT 0 g Output Deviation from Ideal 0 g Offset vs. Temperature for X-, Y-Axes 0 g Offset vs. Temperature for Z-Axis NOISE X-, Y-Axes -150 +150 Z-Axis OUTPUT DATA RATE AND BANDWIDTH Output Data Rate (ODR) 4, 5, 6 SELF-TEST 7 Output Change in X-Axis Output Change in Y-Axis Output Change in Z-Axis POWER SUPPLY Operating Voltage Range (VS) Interface Voltage Range (VDD I/O) Measurement Mode Supply Current Standby Mode Supply Current Turn-On and Wake-Up Time 8 ODR = 100 Hz for 2 g, 10-bit resolution or all g ranges, full resolution ODR = 100 Hz for 2 g, 10-bit resolution or all g ranges, full resolution User selectable 0.10 0.27 -1.55 0.40 1.7 1.7 ODR 100 Hz ODR < 10 Hz ODR = 3200 Hz Rev. 0 | Page 3 of 40 1.5 LSB rms 3200 1.55 -0.27 1.95 2.6 1.8 140 30 0.2 1.4 2.75 VS Hz g g g V V A A A ms ADXL346 Parameter TEMPERATURE Operating Temperature Range WEIGHT Device Weight 1 2 Test Conditions Min 1 -40 Typ 2 Max1 +85 Unit C mg 18 All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed. The typical specifications shown are for at least 68% of the population of parts and are based on the worst case of mean 1 except for 0 g output and sensitivity, which represents the target value. For 0 g offset and sensitivity, the deviation from the ideal describes the worst case of mean 1 . 3 Cross-axis sensitivity is defined as coupling between any two axes. 4 Bandwidth is the -3 dB frequency and is half the output data rate bandwidth = ODR/2. 5 The output format for the 3200 Hz and 1600 Hz ODRs is different from the output format for the remaining ODRs. This difference is described in the Data Formatting of Upper Data Rates section. 6 Output data rates below 6.25 Hz exhibit additional offset shift with increased temperature, depending on selected output data rate. Refer to the Offset Performance at Lowest Data Rates section for details. 7 Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (in the DATA_FORMAT register, Address 0x31) minus the output (g) when the SELF_TEST bit = 0. Due to device filtering, the output reaches its final value after 4 x when enabling or disabling self-test, where = 1/(data rate). The part must be in normal power operation (LOW_POWER bit = 0 in the BW_RATE register, Address 0x2C) for self-test to operate correctly. 8 Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For other data rates, the turn-on and wake-up times are each approximately + 1.1 in milliseconds, where = 1/(data rate). Rev. 0 | Page 4 of 40 ADXL346 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Acceleration Any Axis, Unpowered Any Axis, Powered VS VDD I/O Digital Pins All Other Pins Output Short-Circuit Duration (Any Pin to Ground) Temperature Range Powered Storage Rating 10,000 g 10,000 g -0.3 V to +3.0 V -0.3 V to +3.0 V -0.3 V to VDD I/O + 0.3 V or 3.0 V, whichever is less -0.3 V to +3.0 V Indefinite PACKAGE INFORMATION The information in Figure 2 and Table 4 provide details about the package branding for ADXL346. For a complete listing of product availability, see the Ordering Guide section. Y2Z 08167-047 vvvv Table 4. Package Branding Information Branding Key Y2Z vvvv Figure 2. Product Information on Package (Top View) -40C to +105C -40C to +105C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Field Description Part identifier for ADXL346 Factory lot code ESD CAUTION THERMAL RESISTANCE Table 3. Package Characteristics Package Type 16-Terminal LGA JA 150C/W JC 85C/W Device Weight 18 mg Rev. 0 | Page 5 of 40 ADXL346 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND RESERVED 15 16 14 13 VDD I/O NC NC SCL/SCLK NC 1 2 3 4 5 6 7 8 VS GND GND INT1 NC INT2 ADXL346 +X 12 11 +Y 10 +Z 9 SDO/ ALT ADDRESS SDA/SDI/SDIO NC = NO INTERNAL CONNECTION CS TOP VIEW (Not to Scale) Figure 3. Pin Configuration (Top View) Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic VDD I/O NC NC SCL/SCLK NC SDA/SDI/SDIO SDO/ALT ADDRESS CS INT2 NC INT1 GND GND VS RESERVED GND Description Digital Interface Supply Voltage. Not Internally Connected. Not Internally Connected. Serial Communications Clock. Not Internally Connected. Serial Data (I2C)/Serial Data Input (SPI 4-Wire)/Serial Data Input and Output (SPI 3-Wire). Serial Data Output (SPI 4-Wire)/Alternate I2C Address Select (I2C). Chip Select. Interrupt 2 Output. Not Internally Connected. Interrupt 1 Output. Must be connected to ground. Must be connected to ground. Supply Voltage. Reserved. This pin must be connected to VS. Must be connected to ground. Rev. 0 | Page 6 of 40 08167-002 ADXL346 TYPICAL PERFORMANCE CHARACTERISTICS 30 30 PERCENT OF POPULATION (%) 08167-004 PERCENT OF POPULATION (%) 25 25 20 20 15 15 10 10 5 5 08167-104 0 -150 -100 -50 0 50 ZERO g OFFSET (mg) 100 150 0 -150 -100 -50 0 50 ZERO g OFFSET (mg) 100 150 Figure 4. X-Axis Zero g Offset at 25C, VS = 2.6 V Figure 7. X-Axis Zero g Offset at 25C, VS = 1.8 V 30 30 20 PERCENT OF POPULATION (%) 08167-005 PERCENT OF POPULATION (%) 25 25 20 15 15 10 10 5 5 08167-105 0 -150 -100 -50 0 50 ZERO g OFFSET (mg) 100 150 0 -150 -100 -50 0 50 ZERO g OFFSET (mg) 100 150 Figure 5. Y-Axis Zero g Offset at 25C, VS = 2.6 V Figure 8. Y-Axis Zero g Offset at 25C, VS = 1.8 V 30 30 20 PERCENT OF POPULATION (%) 08167-006 PERCENT OF POPULATION (%) 25 25 20 15 15 10 10 5 5 08167-106 0 -150 -100 -50 0 50 ZERO g OFFSET (mg) 100 150 0 -150 -100 -50 0 50 ZERO g OFFSET (mg) 100 150 Figure 6. Z-Axis Zero g Offset at 25C, VS = 2.6 V Figure 9. Z-Axis Zero g Offset at 25C, VS = 1.8 V Rev. 0 | Page 7 of 40 ADXL346 60 250 200 PERCENT OF POPULATION (%) 50 150 ZERO g OFFSET (mg) 08167-010 40 100 50 0 -50 -100 -150 -200 -250 -40 08167-013 30 20 10 0 -3 -2 -1 0 1 ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/C) -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 10. X-Axis Zero g Offset Temperature Coefficient, VS = 2.6 V Figure 13. X-Axis Zero g Offset vs. Temperature-- Eight Parts Soldered to PCB, VS = 2.6 V 60 250 200 PERCENT OF POPULATION (%) 50 150 ZERO g OFFSET (mg) 40 100 50 0 -50 -100 -150 -200 -250 -40 08167-014 30 20 10 08167-011 0 -3 -2 -1 0 1 ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/C) -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 11. Y-Axis Zero g Offset Temperature Coefficient, VS = 2.6 V Figure 14. Y-Axis Zero g Offset vs. Temperature-- Eight Parts Soldered to PCB, VS = 2.6 V 60 250 200 PERCENT OF POPULATION (%) 50 150 ZERO g OFFSET (mg) 08167-012 40 100 50 0 -50 -100 30 20 10 -150 -200 -250 -40 08167-015 0 -3 -2 -1 0 1 ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/C) -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 12. Z-Axis Zero g Offset Temperature Coefficient, VS = 2.6 V Figure 15. Z-Axis Zero g Offset vs. Temperature-- Eight Parts Soldered to PCB, VS = 2.6 V Rev. 0 | Page 8 of 40 ADXL346 60 60 PERCENT OF POPULATION (%) 40 PERCENT OF POPULATION (%) 08167-016 50 50 40 30 30 20 20 10 10 08167-116 0 230 240 250 260 SENSITIVITY (LSB/g) 270 280 0 230 240 250 260 SENSITIVITY (LSB/g) 270 280 Figure 16. X-Axis Sensitivity at 25C, VS = 2.6 V, Full Resolution Figure 19. X-Axis Sensitivity at 25C, VS = 1.8 V, Full Resolution 60 60 PERCENT OF POPULATION (%) 40 PERCENT OF POPULATION (%) 08167-017 50 50 40 30 30 20 20 10 10 08167-117 0 230 240 250 260 SENSITIVITY (LSB/g) 270 280 0 230 240 250 260 SENSITIVITY (LSB/g) 270 280 Figure 17. Y-Axis Sensitivity at 25C, VS = 2.6 V, Full Resolution Figure 20. Y-Axis Sensitivity at 25C, VS = 1.8 V, Full Resolution 60 60 PERCENT OF POPULATION (%) 50 PERCENT OF POPULATION (%) 08167-018 50 40 40 30 30 20 20 10 10 08167-118 0 230 240 250 260 SENSITIVITY (LSB/g) 270 280 0 230 240 250 260 SENSITIVITY (LSB/g) 270 280 Figure 18. Z-Axis Sensitivity at 25C, VS = 2.6 V, Full Resolution Figure 21. Z-Axis Sensitivity at 25C, VS = 1.8 V, Full Resolution Rev. 0 | Page 9 of 40 ADXL346 100 90 PERCENT OF POPULATION (%) 80 SENSITIVITY (LSB/g) 280 275 270 265 260 255 250 245 240 235 230 -40 08167-025 70 60 50 40 30 20 10 0 -0.10 -0.05 0 0.05 SENSITIVITY TEMPERATURE COEFFICIENT (%/C) 0.10 08167-022 -20 0 20 40 TEMPERATURE (C) 60 80 100 Figure 22. X-Axis Sensitivity Temperature Coefficient, VS = 2.6 V Figure 25. X-Axis Sensitivity vs. Temperature-- Eight Parts Soldered to PCB, VS = 2.6 V, Full Resolution 100 90 PERCENT OF POPULATION (%) 80 280 275 270 SENSITIVITY (LSB/g) 08167-023 70 60 50 40 30 20 10 0 -0.10 -0.05 0 0.05 SENSITIVITY TEMPERATURE COEFFICIENT (%/C) 0.10 265 260 255 250 245 240 235 230 -40 08167-026 -20 0 20 40 TEMPERATURE (C) 60 80 100 Figure 23. Y-Axis Sensitivity Temperature Coefficient, VS = 2.6 V Figure 26. Y-Axis Sensitivity vs. Temperature-- Eight Parts Soldered to PCB, VS = 2.6 V, Full Resolution 100 90 PERCENT OF POPULATION (%) 80 280 275 270 SENSITIVITY (LSB/g) 08167-024 70 60 50 40 30 20 10 0 -0.10 -0.05 0 0.05 SENSITIVITY TEMPERATURE COEFFICIENT (%/C) 0.10 265 260 255 250 245 240 235 230 -40 08167-127 -20 0 20 40 TEMPERATURE (C) 60 80 100 Figure 24. Z-Axis Sensitivity Temperature Coefficient, VS = 2.6 V Figure 27. Z-Axis Sensitivity vs. Temperature-- Eight Parts Soldered to PCB, VS = 2.6 V, Full Resolution Rev. 0 | Page 10 of 40 ADXL346 40 35 PERCENT OF POPULATION (%) 08167-007 40 35 30 25 20 15 10 08167-019 PERCENT OF POPULATION (%) 30 25 20 15 10 5 0 0.5 0.6 0.7 0.8 SELF-TEST SHIFT (g) 0.9 1.0 5 0 90 100 110 120 130 140 150 OUTPUT CURRENT (A) 160 170 180 Figure 28. X-Axis Self-Test Response at 25C, VS = 2.6 V 40 35 PERCENT OF POPULATION (%) Figure 31. Supply Current at 25C, 100 Hz Output Data Rate, VS = 2.6 V 160 140 120 100 80 60 40 08167-020 30 25 20 15 10 08167-008 5 0 -1.0 -0.9 -0.8 -0.7 SELF-TEST SHIFT (g) -0.6 -0.5 SUPPLY CURRENT (A) 20 0 3.13 6.25 12.50 25 50 100 200 400 OUTPUT DATA RATE (Hz) 800 1600 3200 Figure 29. Y-Axis Self-Test Response at 25C, VS = 2.6 V 40 35 PERCENT OF POPULATION (%) Figure 32. Supply Current vs. Output Data Rate at 25C--10 Parts, VS = 2.6 V 150 SUPPLY CURRENT CONSUMPTION (A) 140 30 25 20 15 10 08167-009 130 120 110 5 0 1.0 1.1 1.2 1.3 SELF-TEST SHIFT (g) 1.4 1.5 100 08167-021 90 1.6 1.8 2.0 2.2 2.4 SUPPLY VOLTAGE, VS (V) 2.6 2.8 Figure 30. Z-Axis Self-Test Response at 25C, VS = 2.6 V Figure 33. Supply Current vs. Supply Voltage at 25C Rev. 0 | Page 11 of 40 ADXL346 THEORY OF OPERATION The ADXL346 is a complete 3-axis acceleration measurement system with a selectable measurement range of 2 g, 4 g, 8 g, or 16 g. It measures both dynamic acceleration resulting from motion or shock and static acceleration, such as gravity, which allows the device to be used as a tilt sensor. The sensor is a polysilicon surface-micromachined structure built on top of a silicon wafer. Polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against forces due to applied acceleration. Deflection of the structure is measured using differential capacitors that consist of independent fixed plates and plates attached to the moving mass. Acceleration deflects the proof mass and unbalances the differential capacitor, resulting in a sensor output with an amplitude proportional to acceleration. Phase-sensitive demodulation is used to determine the magnitude and polarity of the acceleration. POWER SEQUENCING Power can be applied to VS or VDD I/O in any sequence without damaging the ADXL346. All possible power-on modes are summarized in Table 6. The interface voltage level is set with the interface supply voltage, VDD I/O, which must be present to ensure that the ADXL346 does not create a conflict on the communication bus. For single-supply operation, VDD I/O can be the same as the main supply, VS. In a dual-supply application, however, VDD I/O can differ from VS to accommodate the desired interface voltage, as long as VS is greater than or equal to VDD I/O. After VS is applied, the device enters standby mode, where power consumption is minimized and the device waits for VDD I/O to be applied and for the command to enter measurement mode to be received. (This command can be initiated by setting the measure bit (Bit D3) in the POWER_CTL register (Address 0x2D).) In addition, any register can be written to or read from to configure the part while the device is in standby mode. It is recommended to configure the device in standby mode and then to enable measurement mode. Clearing the measure bit returns the device to the standby mode. Table 6. Power Sequencing Condition Power Off Bus Disabled VS Off On VDD I/O Off Off Description The device is completely off, but there is a potential for a communication bus conflict. The device is on in standby mode, but communication is unavailable and will create a conflict on the communication bus. The duration of this state should be minimized during power-up to prevent a conflict. No functions are available, but the device will not create a conflict on the communication bus. At power-up, the device is in standby mode, awaiting a command to enter measurement mode, and all sensor functions are off. After the device is instructed to enter measurement mode, all sensor functions are available. Bus Enabled Standby or Measurement Mode Off On On On Rev. 0 | Page 12 of 40 ADXL346 POWER SAVINGS Power Modes The ADXL346 automatically modulates its power consumption in proportion to its output data rate, as outlined in Table 7. If additional power savings is desired, a lower power mode is available. In this mode, the internal sampling rate is reduced, allowing for power savings in the 12.5 Hz to 400 Hz data rate range at the expense of slightly greater noise. To enter low power mode, set the LOW_POWER bit (Bit D4) in the BW_RATE register (Address 0x2C). The current consumption in low power mode is shown in Table 8 for cases where there is an advantage to using low power mode. Use of low power mode for a data rate not shown in Table 8 does not provide any advantage over the same data rate in normal power mode. Therefore, it is recommended that only data rates listed in Table 8 be used in low power mode. The current consumption values shown in Table 7 and Table 8 are for a VS of 2.6 V. Table 7. Typical Current Consumption vs. Data Rate (TA = 25C, VS = 2.6 V, VDD I/O = 1.8 V) Output Data Rate (Hz) 3200 1600 800 400 200 100 50 25 12.5 6.25 3.13 1.56 0.78 0.39 0.20 0.10 Bandwidth (Hz) 1600 800 400 200 100 50 25 12.5 6.25 3.13 1.56 0.78 0.39 0.20 0.10 0.05 Rate Code 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 IDD (A) 140 90 140 140 140 140 90 55 40 31 27 23 23 23 23 23 Table 8. Typical Current Consumption vs. Data Rate, Low Power Mode (TA = 25C, VS = 2.6 V, VDD I/O = 1.8 V) Output Data Rate (Hz) 400 200 100 50 25 12.5 Bandwidth (Hz) 200 100 50 25 12.5 6.25 Rate Code 1100 1011 1010 1001 1000 0111 IDD (A) 90 55 40 31 27 23 Autosleep Mode Additional power can be saved if the ADXL346 automatically switches to sleep mode during periods of inactivity. To enable this feature, set the THRESH_INACT register (Address 0x25) and the TIME_INACT register (Address 0x26) each to a value that signifies inactivity (the appropriate value depends on the application), and then set the AUTO_SLEEP bit (Bit D4) and the link bit (Bit D5) in the POWER_CTL register (Address 0x2D). Current consumption at the sub-8 Hz data rates used in this mode is typically 23 A for a VS of 2.6 V. Standby Mode For even lower power operation, standby mode can be used. In standby mode, current consumption is reduced to 0.2 A (typical). In this mode, no measurements are made. Standby mode is entered by clearing the measure bit (Bit D3) in the POWER_CTL register (Address 0x2D). Placing the device into standby mode preserves the contents of FIFO. Rev. 0 | Page 13 of 40 ADXL346 SERIAL COMMUNICATIONS I2C and SPI digital communications are available. In both cases, the ADXL346 operates as a slave. I2C mode is enabled if the CS pin is tied high to VDD I/O. The CS pin should always be tied high to VDD I/O or be driven by an external controller because there is no default mode if the CS pin is left unconnected. Therefore, not taking these precautions may result in an inability to communicate with the part. In SPI mode, the CS pin is controlled by the bus master. In both SPI and I2C modes of operation, data transmitted from the ADXL346 to the master device should be ignored during writes to the ADXL346. CS is the serial port enable line and is controlled by the SPI master. This line must go low at the start of a transmission and high at the end of a transmission, as shown in Figure 36. SCLK is the serial port clock and is supplied by the SPI master. SCLK should idle high during a period of no transmission. SDI and SDO are the serial data input and output, respectively. Data is updated on the falling edge of SCLK and should be sampled on the rising edge of SCLK. To read or write multiple bytes in a single transmission, the multiple-byte bit, located after the R/W bit in the first byte transfer (MB in Figure 36 to Figure 38), must be set. After the register addressing and the first byte of data, each subsequent set of clock pulses (eight clock pulses) causes the ADXL346 to point to the next register for a read or write. This shifting continues until the clock pulses cease and CS is deasserted. To perform reads or writes on different, nonsequential registers, CS must be deasserted between transmissions and the new register must be addressed separately. The timing diagram for 3-wire SPI reads or writes is shown in Figure 38. The 4-wire equivalents for SPI writes and reads are shown in Figure 36 and Figure 37, respectively. For correct operation of the part, the logic thresholds and timing parameters in Table 9 and Table 10 must be met at all times. Use of the 3200 Hz and 1600 Hz output data rates is recommended only with SPI communication rates greater than or equal to 2 MHz. The 800 Hz output data rate is recommended only for communication speeds greater than or equal to 400 kHz, and the remaining data rates scale proportionally. For example, the minimum recommended communication speed for a 200 Hz output data rate is 100 kHz. Operation at an output data rate above the recommended maximum may result in undesirable effects on the acceleration data, including missing samples or additional noise. SPI For SPI, either 3- or 4-wire configuration is possible, as shown in the connection diagrams in Figure 34 and Figure 35. Clearing the SPI bit (Bit D6) in the DATA_FORMAT register (Address 0x31) selects 4-wire mode, whereas setting the SPI bit selects 3-wire mode. The maximum SPI clock speed is 5 MHz with 100 pF maximum loading, and the timing scheme follows clock polarity (CPOL) = 1 and clock phase (CPHA) = 1. If power is applied to the ADXL346 before the clock polarity and phase of the host processor are configured, the CS pin should be brought high before changing the clock polarity and phase. When using 3-wire SPI, it is recommended that the SDO pin either be pulled up to VDD I/O or be pulled down to GND via a 10 k resistor. ADXL346 CS SDIO SDO SCLK D OUT PROCESSOR D OUT D IN/OUT 08167-027 08167-028 Figure 34. 3-Wire SPI Connection Diagram ADXL346 CS SDI SDO SCLK PROCESSOR D OUT D OUT D IN D OUT Figure 35. 4-Wire SPI Connection Diagram Rev. 0 | Page 14 of 40 ADXL346 CS tDELAY SCLK tSCLK tM tS tQUIET tCS,DIS tSETUP SDI W tHOLD MB A5 A0 D7 D0 tSDO SDO X X ADDRESS BITS X X DATA BITS X tDIS X 08167-129 tR, tF Figure 36. SPI 4-Wire Write CS tDELAY SCLK tSCLK tM tS tQUIET tCS,DIS tSETUP SDI R tHOLD MB A5 A0 X X tSDO SDO X X ADDRESS BITS X X D7 tDIS D0 08167-130 tR, tF DATA BITS Figure 37. SPI 4-Wire Read CS tDELAY SCLK tSCLK tM tS tQUIET tCS,DIS tSETUP SDIO R/W tHOLD MB A5 tR, tF A0 D7 tSDO D0 ADDRESS BITS SDO NOTES 1. tSDO IS ONLY PRESENT DURING READS. DATA BITS Figure 38. SPI 3-Wire Read/Write Rev. 0 | Page 15 of 40 08167-131 ADXL346 Table 9. SPI Digital Input/Output Parameter Digital Input Low Level Input Voltage (VIL) High Level Input Voltage (VIH) Low Level Input Current (IIL) High Level Input Current (IIH) Digital Output Low Level Output Voltage (VOL) High Level Output Voltage (VOH) Low Level Output Current (IOL) High Level Output Current (IOH) Pin Capacitance 1 Test Conditions Min Limit 1 Max 0.3 x VDD I/O Unit V V A A V V mA mA pF 0.7 x VDD I/O VIN = VDD I/O VIN = 0 V IOL = 10 mA IOH = -4 mA VOL = VOL, max VOH = VOH, min fIN = 1 MHz, VIN = 2.6 V 0.1 -0.1 0.2 x VDD I/O 0.8 x VDD I/O 10 -4 8 Limits are based on characterization results; not production tested. Table 10. SPI Timing (TA = 25C, VS = 2.6 V, VDD I/O = 1.8 V) 1 Parameter fSCLK tSCLK tDELAY tQUIET tDIS tCS,DIS tS tM tSETUP tHOLD tSDO tR 4 tF4 1 2 Min 200 5 5 Limit 2, 3 Max 5 10 150 0.3 x tSCLK 0.3 x tSCLK 5 5 40 20 20 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns Description SPI clock frequency 1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40 CS falling edge to SCLK falling edge SCLK rising edge to CS rising edge CS rising edge to SDO disabled CS deassertion between SPI communications SCLK low pulse width (space) SCLK high pulse width (mark) SDI valid before SCLK rising edge SDI valid after SCLK rising edge SCLK falling edge to SDO/SDIO output transition SDO/SDIO output low to output high transition SDO/SDIO output high to output low transition The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation. Limits are based on characterization results; not production tested. 3 The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 9. 4 Output rise and fall times are measured with a capacitive load of 150 pF. Rev. 0 | Page 16 of 40 ADXL346 I2C With CS tied high to VDD I/O, the ADXL346 is in I2C mode, requiring a simple 2-wire connection as shown in Figure 39. The ADXL346 conforms to the UM10204 I2C-Bus Specification and User Manual, Rev. 03--19 June 2007, available from NXP Semiconductor. It supports standard (100 kHz) and fast (400 kHz) data transfer modes if the bus parameters given in Table 11 and Table 12 are met. Single- or multiple-byte reads/writes are supported, as shown in Figure 40. With the ALT ADDRESS pin (Pin 7) high, the 7-bit I2C address for the device is 0x1D, followed by the R/W bit. This translates to 0x3A for a write and 0x3B for a read. An alternate I2C address of 0x53 (followed by the R/W bit) can be chosen by grounding the ALT ADDRESS pin. This translates to 0xA6 for a write and 0xA7 for a read. There are no internal pull-up or pull-down resistors for any unused pins; therefore, there is no known state or default state for the CS or ALT ADDRESS pin if left floating or unconnected. It is required that the CS pin be connected to VDD I/O and that the ALT ADDRESS pin be connected to either VDD I/O or GND when using I2C. Due to communication speed limitations, the maximum output data rate when using 400 kHz I2C is 800 Hz and scales linearly with a change in the I2C communication speed. For example, using I2C at 100 kHz would limit the maximum ODR to 200 Hz. Operation at an output data rate above the recommended maximum may result in an undesirable effect on the acceleration data, including missing samples or additional noise. VDD I/O ADXL346 CS SDA ALT ADDRESS RP RP PROCESSOR D IN/OUT Figure 39. I2C Connection Diagram (Address 0x53) If other devices are connected to the same I2C bus, the nominal operating voltage level of these other devices cannot exceed VDD I/O by more than 0.3 V. External pull-up resistors, RP, are necessary for proper I2C operation. Refer to the UM10204 I2C-Bus Specification and User Manual, Rev. 03--19 June 2007, when selecting pull-up resistor values to ensure proper operation. Table 11. I2C Digital Input/Output Parameter Digital Input Low Level Input Voltage (VIL) High Level Input Voltage (VIH) Low Level Input Current (IIL) High Level Input Current (IIH) Digital Output Low Level Output Voltage (VOL) Low Level Output Current (IOL) Pin Capacitance 1 Test Conditions Min Limit 1 Max 0.3 x VDD I/O 08167-032 SCL D OUT Unit V V A A V mV mA pF 0.7 x VDD I/O VIN = VDD I/O VIN = 0 V VDD I/O < 2 V, IOL = 3 mA VDD I/O 2 V, IOL = 3 mA VOL = VOL, max fIN = 1 MHz, VIN = 2.6 V 0.1 -0.1 0.2 x VDD I/O 400 3 8 Limits are based on characterization results; not production tested. SINGLE-BYTE WRITE MASTER START SLAVE SLAVE ADDRESS + WRITE ACK REGISTER ADDRESS ACK DATA ACK STOP MULTIPLE-BYTE WRITE MASTER START SLAVE SLAVE ADDRESS + WRITE ACK REGISTER ADDRESS ACK DATA ACK DATA ACK STOP SINGLE-BYTE READ MASTER START SLAVE SLAVE ADDRESS + WRITE ACK REGISTER ADDRESS ACK START1 SLAVE ADDRESS + READ ACK DATA NACK STOP MULTIPLE-BYTE READ MASTER START SLAVE SLAVE ADDRESS + WRITE ACK REGISTER ADDRESS ACK START1 SLAVE ADDRESS + READ ACK DATA ACK DATA NACK STOP 1THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START. 08167-033 NOTES 1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING. Figure 40. I2C Device Addressing Rev. 0 | Page 17 of 40 ADXL346 Table 12. I2C Timing (TA = 25C, VS = 2.6 V, VDD I/O = 1.8 V) Parameter fSCL t1 t2 t3 t4 t5 t6 3, 4, 5, 6 t7 t8 t9 t10 t11 20 + 0.1 CB 7 CB 1 2 Min 2.5 0.6 1.3 0.6 100 0 0.6 0.6 1.3 0 Limit 1, 2 Max 400 0.9 300 250 300 400 7 Unit kHz s s s s ns s s s s ns ns ns ns ns pF Description SCL clock frequency SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD, STA, start/repeated start condition hold time tSU, DAT, data setup time tHD, DAT, data hold time tSU, STA, setup time for repeated start tSU, STO, stop condition setup time tBUF, bus-free time between a stop condition and a start condition tR, rise time of both SCL and SDA when receiving tR, rise time of both SCL and SDA when receiving or transmitting tF, fall time of SDA when receiving tF, fall time of both SCL and SDA when transmitting tF, fall time of both SCL and SDA when transmitting or receiving Capacitive load for each bus line Limits are based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested. All values referred to the VIH and the VIL levels given in Table 11. 3 t6 is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge. 4 A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to VIH,min of the SCL signal) to bridge the undefined region of the falling edge of SCL. 5 The maximum t6 value must be met only if the device does not stretch the low period (t3) of the SCL signal. 6 The maximum value for t6 is a function of the clock low time (t3), the clock rise time (t10), and the minimum data setup time (t5(min)). This value is calculated as t6(max) = t3 - t10 - t5(min). 7 CB is the total capacitance of one bus line in picofarads. SDA t9 t3 t10 t11 t4 SCL t4 START CONDITION t6 t2 t5 t7 REPEATED START CONDITION t1 t8 STOP CONDITION 08167-034 Figure 41. I2C Timing Diagram Rev. 0 | Page 18 of 40 ADXL346 INTERRUPTS The ADXL346 provides two output pins for driving interrupts: INT1 and INT2. Both interrupt pins are push-pull, low impedance pins with the output specifications listed in Table 13. The default configuration of the interrupt pins is active high. This can be changed to active low by setting the INT_INVERT bit (Bit D5) in the DATA_FORMAT (Address 0x31) register. All functions can be used simultaneously, with the only limiting feature being that some functions may need to share interrupt pins. Interrupts are enabled by setting the appropriate bit in the INT_ENABLE register (Address 0x2E) and are mapped to either the INT1 or INT2 pin based on the contents of the INT_MAP register (Address 0x2F). When initially configuring the interrupt pins, it is recommended that the functions and interrupt mapping be done before enabling the interrupts. When changing the configuration of an interrupt, it is recommended that the interrupt be disabled first, by clearing the bit corresponding to that function in the INT_ENABLE register, and then the function be reconfigured before enabling the interrupt again. Configuration of the functions while the interrupts are disabled helps to prevent the accidental generation of an interrupt before it is desired. The interrupt functions are latched and cleared by either reading the DATAX, DATAY, and DATAZ registers (Address 0x32 to Address 0x37) until the interrupt condition is no longer valid for the data-related interrupts or by reading the INT_SOURCE register (Address 0x30) for the remaining interrupts. This section describes the interrupts that can be set in the INT_ENABLE register and monitored in the INT_SOURCE register. DOUBLE_TAP Bit The DOUBLE_TAP bit is set when two acceleration events that are greater than the value in the THRESH_TAP register (Address 0x1D) occur for less time than is specified in the DUR register (Address 0x21). The second tap starts after the time specified by the latent register (Address 0x22) but within the time specified in the window register (Address 0x23). See the Tap Detection section for more details. Activity Bit The activity bit is set when acceleration greater than the value stored in the THRESH_ACT register (Address 0x24) is experienced on any participating axis, as set by the ACT_INACT_CTL register (Address 0x27). Inactivity Bit The inactivity bit is set when acceleration of less than the value stored in the THRESH_INACT register (Address 0x25) is experienced for more time than is specified in the TIME_INACT register (Address 0x26) on all participating axes, as set by the ACT_INACT_CTL register (Address 0x27). The maximum value for TIME_INACT is 255 sec. FREE_FALL Bit The FREE_FALL bit is set when acceleration of less than the value stored in the THRESH_FF register (Address 0x28) is experienced for more time than is specified in the TIME_FF register (Address 0x29) on all axes (logical AND). The FREE_FALL interrupt differs from the inactivity interrupt as follows: all axes always participate and are logically AND'ed, the timer period is much smaller (1.28 sec maximum), and the mode of operation is always dc-coupled. DATA_READY Bit The DATA_READY bit is set when new data is available and is cleared when no new data is available. Watermark Bit The watermark bit is set when the number of samples in FIFO equals the value stored in the samples bits (Register FIFO_CTL, Address 0x38). The watermark bit is cleared automatically when FIFO is read, and the content returns to a value below the value stored in the samples bits. SINGLE_TAP Bit The SINGLE_TAP bit is set when a single acceleration event that is greater than the value in the THRESH_TAP register (Address 0x1D) occurs for less time than is specified in the DUR register (Address 0x21). Table 13. Interrupt Pin Digital Output Parameter Digital Output Low Level Output Voltage (VOL) High Level Output Voltage (VOH) Low Level Output Current (IOL) High Level Output Current (IOH) Pin Capacitance Rise/Fall Time Rise Time (tR) 2 Fall Time (tF) 3 1 2 Test Conditions IOL = 300 A IOH = -150 A VOL = VOL, max VOH = VOH, min fIN = 1 MHz, VIN = 2.6 V CLOAD = 150 pF CLOAD = 150 pF Min Limit 1 Max 0.2 x VDD I/O Unit V V A A pF ns ns 0.8 x VDD I/O 300 -150 8 210 150 Limits are based on characterization results; not production tested. Rise time is measured as the transition time from VOL, max to VOH, min of the interrupt pin. 3 Fall time is measured as the transition time from VOH, min to VOL, max of the interrupt pin. Rev. 0 | Page 19 of 40 ADXL346 Overrun Bit The overrun bit is set when new data replaces unread data. The precise operation of the overrun function depends on the FIFO mode. In bypass mode, the overrun bit is set when new data replaces unread data in the DATAX, DATAY, and DATAZ registers (Address 0x32 to Address 0x37). In all other modes, the overrun bit is set when FIFO is filled. The overrun bit is automatically cleared when the contents of FIFO are read. Stream Mode In stream mode, data from measurements of the x-, y-, and zaxes are stored in FIFO. When the number of samples in FIFO equals the level specified in the samples bits of the FIFO_CTL register (Address 0x38), the watermark interrupt is set. FIFO continues accumulating samples and holds the latest 32 samples from measurements of the x-, y-, and z-axes, discarding older data as new data arrives. The watermark interrupt continues occurring until the number of samples in FIFO is less than the value stored in the samples bits of the FIFO_CTL register. Orientation Bit The orientation bit is set when the orientation of the accelerometer changes from a valid orientation to a different valid orientation. An interrupt is not generated, however, if the orientation of the accelerometer changes from a valid orientation to an invalid orientation, or from a valid orientation to an invalid orientation and then back to the same valid orientation. An invalid orientation is defined as an orientation within the dead zone, or the region of hysteresis. This region helps to prevent rapid orientation change due to noise when the accelerometer orientation is close to the boundary between two valid orientations. The orientations that are valid for the interrupt depend on which mode, 2D or 3D, is linked to the orientation interrupt. The mode is selected with the INT_3D bit (Bit D3) in the ORIENT_CONF register (Address 0x3B). See the Register 0x3B--ORIENT_CONF (Read/Write) section for more details on how to enable the orientation interrupt. Trigger Mode In trigger mode, FIFO accumulates samples, holding the latest 32 samples from measurements of the x-, y-, and z-axes. After a trigger event occurs and an interrupt is sent to the INT1 or INT2 pin (determined by the trigger bit in the FIFO_CTL register), FIFO keeps the last n samples (where n is the value specified by the samples bits in the FIFO_CTL register) and then operates in FIFO mode, collecting new samples only when FIFO is not full. A delay of at least 5 s should be present between the trigger event occurring and the start of reading data from the FIFO to allow the FIFO to discard and retain the necessary samples. Additional trigger events cannot be recognized until the trigger mode is reset. To reset the trigger mode, set the device to bypass mode and then set the device back to trigger mode. Note that the FIFO data should be read first because placing the device into bypass mode clears FIFO. FIFO The ADXL346 contains patent pending technology for an embedded memory management system with 32-level FIFO that can be used to minimize host processor burden. This buffer has four modes: bypass, FIFO, stream, and trigger (see Table 22). Each mode is selected by the settings of the FIFO_MODE bits (Bits[D7:D6]) in the FIFO_CTL register (Address 0x38). Retrieving Data from FIFO The FIFO data is read through the DATAX, DATAY, and DATAZ registers (Address 0x32 to Address 0x37). When the FIFO is in FIFO, stream, or trigger mode, reads to the DATAX, DATAY, and DATAZ registers read data stored in the FIFO. Each time data is read from the FIFO, the oldest x-, y-, and z-axes data are placed into the DATAX, DATAY, and DATAZ registers. If a single-byte read operation is performed, the remaining bytes of data for the current FIFO sample are lost. Therefore, all axes of interest should be read in a burst (or multiple-byte) read operation. To ensure that the FIFO has completely popped (that is, that new data has completely moved into the DATAX, DATAY, and DATAZ registers), there must be at least 5 s between the end of reading the data registers and the start of a new read of the FIFO or a read of the FIFO_STATUS register (Address 0x39). The end of reading a data register is signified by the transition of data from Register 0x37 to Register 0x38 or by the CS pin going high. For SPI operation at 1.6 MHz or less, the register addressing portion of the transmission is a sufficient delay to ensure that the FIFO has completely popped. For SPI operation greater than 1.6 MHz, it is necessary to deassert the CS pin to ensure a total delay of 5 s; otherwise, the delay will not be sufficient. The total delay necessary for 5 MHz operation is at most 3.4 s. This is not a concern when using I2C mode because the communication rate is low enough to ensure a sufficient delay between FIFO reads. Bypass Mode In bypass mode, FIFO is not operational and, therefore, remains empty. FIFO Mode In FIFO mode, data from measurements of the x-, y-, and z-axes are stored in FIFO. When the number of samples in FIFO equals the level specified in the samples bits of the FIFO_CTL register (Address 0x38), the watermark interrupt is set. FIFO continues accumulating samples until it is full (32 samples from measurements of the x-, y-, and z-axes) and then stops collecting data. After FIFO stops collecting data, the device continues to operate; therefore, features such as tap detection can be used after FIFO is full. The watermark interrupt continues to occur until the number of samples in FIFO is less than the value stored in the samples bits of the FIFO_CTL register. Rev. 0 | Page 20 of 40 ADXL346 SELF-TEST The ADXL346 incorporates a self-test feature that effectively tests its mechanical and electronic systems simultaneously. When the self-test function is enabled (via the SELF_TEST bit (Bit D7 in the DATA_FORMAT register, Address 0x31), an electrostatic force is exerted on the mechanical sensor. This electrostatic force moves the mechanical sensing element in the same manner as acceleration would, and it is additive to the acceleration experienced by the device. This added electrostatic force results in an output change in the x-, y-, and z-axes. Because the electrostatic force is proportional to VS2, the output change varies with VS. This effect is shown in Figure 42. The scale factors listed in Table 14 can be used to adjust the expected self-test output limits for different supply voltages, VS. The self-test feature of the ADXL346 also exhibits a bimodal behavior. However, the limits listed in Table 1 and Table 15 to Table 18 are valid for both potential self-test values due to bimodality. Use of the self-test feature at data rates less than 100 Hz or at 1600 Hz may yield values outside these limits. Therefore, the part must be in normal power operation (LOW_POWER bit = 0 in the BW_RATE register, Address 0x2C) and be placed into a data rate of 100 Hz through 800 Hz or 3200 Hz for the self-test function to operate correctly. 3 X-AXIS SELF-TEST HIGH LIMIT Y-AXIS SELF-TEST HIGH LIMIT Z-AXIS SELF-TEST HIGH LIMIT X-AXIS SELF-TEST LOW LIMIT Y-AXIS SELF-TEST LOW LIMIT Z-AXIS SELF-TEST LOW LIMIT Table 14. Self-Test Output Scale Factors for Different Supply Voltages, VS Supply Voltage, VS 1.70 V 1.80 V 2.00 V 2.60 V 2.75 V X-, Y-Axes 0.43 0.48 0.59 1.00 1.13 Z-Axis 0.38 0.47 0.58 1.00 1.11 Table 15. Self-Test Output in LSB for 2 g, 10-Bit or Full Resolution (TA = 25C, VS = 2.6 V, VDD I/O = 1.8 V) Axis X Y Z Min 70 -400 100 Max 400 -70 500 Unit LSB LSB LSB Table 16. Self-Test Output in LSB for 4 g, 10-Bit Resolution (TA = 25C, VS = 2.6 V, VDD I/O = 1.8 V) Axis X Y Z Min 35 -200 50 Max 200 -35 250 Unit LSB LSB LSB Table 17. Self-Test Output in LSB for 8 g, 10-Bit Resolution (TA = 25C, VS = 2.6 V, VDD I/O = 1.8 V) Axis X Y Z Min 17 -100 25 Max 100 -17 125 Unit LSB LSB LSB 2 SELF-TEST SHIFT LIMITS (g) 1 0 Table 18. Self-Test Output in LSB for 16 g, 10-Bit Resolution (TA = 25C, VS = 2.6 V, VDD I/O = 1.8 V) Axis X Y Z Min 8 -50 12 Max 50 -8 63 Unit LSB LSB LSB -1 -2 08167-136 -3 1.6 1.8 2.0 2.2 2.4 SUPPLY VOLTAGE, VS (V) 2.6 2.8 Figure 42. Self-Test Output Change Limits vs. Supply Voltage Rev. 0 | Page 21 of 40 ADXL346 REGISTER MAP Table 19. Register Map Address Hex Dec 0x00 0 0x01 to 0x1C 1 to 28 0x1D 29 0x1E 30 0x1F 31 0x20 32 0x21 33 0x22 34 0x23 35 0x24 36 0x25 37 0x26 38 0x27 39 0x28 40 0x29 41 0x2A 42 0x2B 43 0x2C 44 0x2D 45 0x2E 46 0x2F 47 0x30 48 0x31 49 0x32 50 0x33 51 0x34 52 0x35 53 0x36 54 0x37 55 0x38 56 0x39 57 0x3A 58 0x3B 59 0x3C 60 Name DEVID Reserved THRESH_TAP OFSX OFSY OFSZ DUR Latent Window THRESH_ACT THRESH_INACT TIME_INACT ACT_INACT_CTL THRESH_FF TIME_FF TAP_AXES ACT_TAP_STATUS BW_RATE POWER_CTL INT_ENABLE INT_MAP INT_SOURCE DATA_FORMAT DATAX0 DATAX1 DATAY0 DATAY1 DATAZ0 DATAZ1 FIFO_CTL FIFO_STATUS TAP_SIGN ORIENT_CONF Orient Type R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R R R R R R R/W R R R/W R Reset Value 11100110 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00001010 00000000 00000000 00000000 00000010 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00100101 00000000 Description Device ID. Reserved. Do not access. Tap threshold. X-axis offset. Y-axis offset. Z-axis offset. Tap duration. Tap latency. Tap window. Activity threshold. Inactivity threshold. Inactivity time. Axis enable control for activity and inactivity detection. Free-fall threshold. Free-fall time. Axis control for single tap/double tap. Source of single tap/double tap. Data rate and power mode control. Power-saving features control. Interrupt enable control. Interrupt mapping control. Source of interrupts. Data format control. X-Axis Data 0. X-Axis Data 1. Y-Axis Data 0. Y-Axis Data 1. Z-Axis Data 0. Z-Axis Data 1. FIFO control. FIFO status. Sign and source for single tap/double tap. Orientation configuration. Orientation status. Rev. 0 | Page 22 of 40 ADXL346 REGISTER DEFINITIONS Register 0x00--DEVID (Read Only) D7 1 D6 1 D5 1 D4 0 D3 0 D2 1 D1 1 D0 0 Register 0x24--THRESH_ACT (Read/Write) The THRESH_ACT register is eight bits and holds the threshold value for detecting activity. The data format is unsigned, so the magnitude of the activity event is compared with the value in the THRESH_ACT register. The scale factor is 62.5 mg/LSB. A value of 0 may result in undesirable behavior if the activity interrupt is enabled. The DEVID register holds a fixed device ID code of 0xE6 (346 octal). Register 0x1D--THRESH_TAP (Read/Write) The THRESH_TAP register is eight bits and holds the threshold value for tap interrupts. The data format is unsigned, so the magnitude of the tap event is compared with the value in THRESH_TAP for normal tap detection. For information on improved tap detection, refer to the Improved Tap Detection section. The scale factor is 62.5 mg/LSB (that is, 0xFF = +16 g). A value of 0 may result in undesirable behavior if single-tap/ double-tap interrupts are enabled. Register 0x25--THRESH_INACT (Read/Write) The THRESH_INACT register is eight bits and holds the threshold value for detecting inactivity. The data format is unsigned, so the magnitude of the inactivity event is compared with the value in the THRESH_INACT register. The scale factor is 62.5 mg/LSB. A value of 0 may result in undesirable behavior if the inactivity interrupt is enabled. Register 0x26--TIME_INACT (Read/Write) The TIME_INACT register is eight bits and contains an unsigned time value representing the amount of time that acceleration must be less than the value in the THRESH_INACT register for inactivity to be declared. The scale factor is 1 sec/LSB. Unlike the other interrupt functions, which use unfiltered data (see the Threshold section), the inactivity function uses filtered output data. At least one output sample must be generated for the inactivity interrupt to be triggered. This results in the function appearing unresponsive if the TIME_INACT register is set to a value less than the time constant of the output data rate. A value of 0 results in an interrupt when the output data is less than the value in the THRESH_INACT register. Register 0x1E, Register 0x1F, Register 0x20--OFSX, OFSY, OFSZ (Read/Write) The OFSX, OFSY, and OFSZ registers are each eight bits and offer user-set offset adjustments in twos complement format with a scale factor of 15.6 mg/LSB (that is, 0x7F = 2 g). The values stored in the offset registers are automatically added to the acceleration data, and the resulting value is stored in the output data registers. For additional information regarding offset calibration and the use of the offset registers, refer to the Offset Calibration section. Register 0x21--DUR (Read/Write) The DUR register is eight bits and contains an unsigned time value representing the maximum time that an event must be above the THRESH_TAP threshold to qualify as a tap event. For information on improved tap detection, refer to the Improved Tap Detection section. The scale factor is 625 s/LSB. A value of 0 disables the single-tap/double-tap functions. Register 0x27--ACT_INACT_CTL (Read/Write) D7 ACT ac/dc D3 INACT ac/dc D6 ACT_X enable D2 INACT_X enable D5 ACT_Y enable D1 INACT_Y enable D4 ACT_Z enable D0 INACT_Z enable Register 0x22--Latent (Read/Write) The latent register is eight bits and contains an unsigned time value representing the wait time from the detection of a tap event to the start of the time window (defined by the window register) during which a possible second tap event can be detected. For information on improved tap detection, refer to the Improved Tap Detection section. The scale factor is 1.25 ms/LSB. A value of 0 disables the double-tap function. ACT AC/DC and INACT AC/DC Bits A setting of 0 selects dc-coupled operation, and a setting of 1 enables ac-coupled operation. In dc-coupled operation, the current acceleration magnitude is compared directly with THRESH_ACT and THRESH_INACT to determine whether activity or inactivity is detected. In ac-coupled operation for activity detection, the acceleration value at the start of activity detection is taken as a reference value. New samples of acceleration are then compared to this reference value, and if the magnitude of the difference exceeds the THRESH_ACT value, the device triggers an activity interrupt. Similarly, in ac-coupled operation for inactivity detection, a reference value is used for comparison and is updated whenever the device exceeds the inactivity threshold. After the reference value is selected, the device compares the magnitude of the difference between the reference value and the current acceleration with THRESH_INACT. If the difference is less than the value in THRESH_INACT for the time in TIME_INACT, the device is considered inactive and the inactivity interrupt is triggered. Register 0x23--Window (Read/Write) The window register is eight bits and contains an unsigned time value representing the amount of time after the expiration of the latency time (determined by the latent register) during which a second valid tap can begin. For information on improved tap detection, refer to the Improved Tap Detection section. The scale factor is 1.25 ms/LSB. A value of 0 disables the double-tap function. Rev. 0 | Page 23 of 40 ADXL346 ACT_x Enable Bits and INACT_x Enable Bits A setting of 1 enables x-, y-, or z-axis participation in detecting activity or inactivity. A setting of 0 excludes the selected axis from participation. If all axes are excluded, the function is disabled. For activity detection, all participating axes are logically OR'ed, causing the activity function to trigger when any of the participating axes exceeds the threshold. For inactivity detection, all participating axes are logically AND'ed, causing the inactivity function to trigger only if all participating axes are below the threshold for the specified period of time. Register 0x2B--ACT_TAP_STATUS (Read Only) D7 0 D6 ACT_X source D5 ACT_Y source D4 ACT_Z source D3 Asleep D2 TAP_X source D1 TAP_Y source D0 TAP_Z source ACT_x Source and TAP_x Source Bits These bits indicate the first axis involved in a tap or activity event. A setting of 1 corresponds to involvement in the event, and a setting of 0 corresponds to no involvement. When new data is available, these bits are not cleared but are overwritten by the new data. The ACT_TAP_STATUS register should be read before clearing the interrupt. Disabling an axis from participation clears the corresponding source bit when the next activity or single-tap/double-tap event occurs. Register 0x28--THRESH_FF (Read/Write) The THRESH_FF register is eight bits and holds the threshold value, in unsigned format, for free-fall detection. The acceleration on all axes is compared with the value in THRESH_FF to determine if a free-fall event occurred. The scale factor is 62.5 mg/LSB. Note that a value of 0 mg may result in undesirable behavior if the free-fall interrupt is enabled. Values between 300 mg and 600 mg (0x05 to 0x09) are recommended. Asleep Bit A setting of 1 in the asleep bit indicates that the part is asleep, and a setting of 0 indicates that the part is not asleep. This bit toggles only if the device is configured for autosleep. See the Register 0x2D--POWER_CTL (Read/Write) section for more information on autosleep mode. Register 0x29--TIME_FF (Read/Write) The TIME_FF register is eight bits and stores an unsigned time value representing the minimum time that the value of all axes must be less than THRESH_FF to generate a free-fall interrupt. The scale factor is 5 ms/LSB. A value of 0 may result in undesirable behavior if the free-fall interrupt is enabled. Values between 100 ms and 350 ms (0x14 to 0x46) are recommended. Register 0x2C--BW_RATE (Read/Write) D7 0 D6 0 D5 0 D4 LOW_POWER D3 D2 D1 Rate D0 LOW_POWER Bit A setting of 0 in the LOW_POWER bit selects normal operation, and a setting of 1 selects reduced power operation, which is associated with somewhat higher noise (see the Power Modes section for details). Register 0x2A--TAP_AXES (Read/Write) D7 0 D6 0 D5 0 D4 Improved tap D3 Suppress D2 TAP_X enable D1 TAP_Y enable D0 TAP_Z enable Rate Bits These bits select the device bandwidth and output data rate (see Table 7 and Table 8 for details). The default value is 0x0A, which translates to a 100 Hz output data rate. An output data rate should be selected that is appropriate for the communication protocol and frequency selected. Selecting too high of an output data rate with a low communication speed results in samples being discarded. Improved Tap Bit The improved tap bit is used to enable improved tap detection. This mode of operation improves tap detection by performing an ac-coupled differential comparison of the output acceleration data. The improved tap detection is performed on the same output data available in the DATAX, DATAY, and DATAZ registers. Due to the dependency on the output data rate and the ac-coupled differential measurement, the threshold and timing values for single taps and double taps must be adjusted for improved tap detection. For further explanation of improved tap detection, see the Improved Tap Detection section. Improved tap is enabled by setting the improved tap bit to a value of 1 and is disabled by clearing the bit to a value of 0. Register 0x2D--POWER_CTL (Read/Write) D7 0 D6 0 D5 Link D4 AUTO_SLEEP D3 Measure D2 Sleep D1 D0 Wakeup Link Bit A setting of 1 in the link bit with both the activity and inactivity functions enabled delays the start of the activity function until inactivity is detected. After activity is detected, inactivity detection begins, preventing the detection of activity. This bit serially links the activity and inactivity functions. When this bit is set to 0, the inactivity and activity functions are concurrent. Additional information can be found in the Link Mode section. Suppress Bit Setting the suppress bit suppresses double-tap detection if acceleration greater than the value in THRESH_TAP is present between taps. See the Tap Detection section for more details. TAP_x Enable Bits A setting of 1 in the TAP_X enable, TAP_Y enable, or TAP_Z enable bit enables x-, y-, or z-axis participation in tap detection. A setting of 0 excludes the selected axis from participation in tap detection. Rev. 0 | Page 24 of 40 ADXL346 When clearing the link bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. This is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the link bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared. Wakeup Bits These bits control the frequency of readings in sleep mode as described in Table 20. Table 20. Frequency of Readings in Sleep Mode D1 0 0 1 1 Setting D0 0 1 0 1 Frequency (Hz) 8 4 2 1 AUTO_SLEEP Bit If the link bit is set, a setting of 1 in the AUTO_SLEEP bit enables the autosleep functionality. In this mode, the ADXL346 automatically switches to sleep mode if the inactivity function is enabled and inactivity is detected (that is, when acceleration is below the THRESH_INACT value for at least the time indicated by TIME_INACT). If activity is also enabled, the ADXL346 automatically wakes up from sleep after detecting activity and returns to operation at the output data rate set in the BW_RATE register. A setting of 0 in the AUTO_SLEEP bit disables automatic switching to sleep mode. See the description of the sleep bit in this section for more information on sleep mode. If the link bit is not set, the AUTO_SLEEP feature is disabled, and setting the AUTO_SLEEP bit does not have any impact on device operation. Refer to the Link Bit section or the Link Mode section for more information about using the link feature. When clearing the AUTO_SLEEP bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. This is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the AUTO_SLEEP bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared. Register 0x2E--INT_ENABLE (Read/Write) D7 DATA_READY D3 Inactivity D6 SINGLE_TAP D2 FREE_FALL D5 DOUBLE_TAP D1 Watermark D4 Activity D0 Overrun/ orientation Setting bits in this register to a value of 1 enables their respective functions to generate interrupts, whereas a value of 0 prevents the functions from generating interrupts. The DATA_READY, watermark, and overrun/orientation bits enable only the interrupt output; the functions are always enabled. It is recommended that interrupts be configured before enabling their outputs. Register 0x2F--INT_MAP (Read/Write) D7 DATA_READY D3 Inactivity D6 SINGLE_TAP D2 FREE_FALL D5 DOUBLE_TAP D1 Watermark D4 Activity D0 Overrun/ orientation Measure Bit A setting of 0 in the measure bit places the part into standby mode, and a setting of 1 places the part into measurement mode. The ADXL346 powers up in standby mode with minimum power consumption. Bits set to 0 in this register send their respective interrupts to the INT1 pin, whereas bits set to 1 send their respective interrupts to the INT2 pin. All selected interrupts for a given pin are OR'ed. Register 0x30--INT_SOURCE (Read Only) D7 DATA_READY D3 Inactivity D6 SINGLE_TAP D2 FREE_FALL D5 DOUBLE_TAP D1 Watermark D4 Activity D0 Overrun/ orientation Sleep Bit A setting of 0 in the sleep bit puts the part into the normal mode of operation, and a setting of 1 places the part into sleep mode. Sleep mode suppresses DATA_READY, stops transmission of data to FIFO, and switches the sampling rate to one specified by the wakeup bits. In sleep mode, only the activity function can be used. While the DATA_READY interrupt is suppressed, the output data registers are still updated at the sampling rate set by the wakeup bits. When clearing the sleep bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. This is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the sleep bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared. Bits set to 1 in this register indicate that their respective functions have triggered an event, whereas bits set to 0 indicate that the corresponding events have not occurred. The DATA_READY, watermark, and overrun/orientation bits are always set if the corresponding events occur, regardless of the INT_ENABLE register settings, and are cleared by reading data from the DATAX, DATAY, and DATAZ registers. The DATA_READY and watermark bits may require multiple reads, as indicated in the FIFO mode descriptions in the FIFO section. Other bits, and the corresponding interrupts, including orientation if enabled, are cleared by reading the INT_SOURCE register. Rev. 0 | Page 25 of 40 ADXL346 Register 0x31--DATA_FORMAT (Read/Write) D7 SELF_TEST D6 SPI D5 INT_INVERT D4 0 D3 FULL_RES D2 Justify D1 D0 Range The DATA_FORMAT register controls the presentation of data to Register 0x32 through Register 0x37. All data, except that for the 16 g range, must be clipped to avoid rollover. and DATAx1 as the most significant byte, where x represents X, Y, or Z. The DATA_FORMAT register (Address 0x31) controls the format of the data. It is recommended that a multiple-byte read of all registers be performed to prevent a change in data between reads of sequential registers. Register 0x38--FIFO_CTL (Read/Write) D7 D6 FIFO_MODE D5 Trigger D4 D3 D2 D1 Samples D0 SELF_TEST Bit A setting of 1 in the SELF_TEST bit applies a self-test force to the sensor, causing a shift in the output data. A value of 0 disables the self-test force. FIFO_MODE Bits These bits set the FIFO mode, as described in Table 22. Table 22. FIFO Modes Setting D7 D6 0 0 0 1 Mode Bypass FIFO Function FIFO is bypassed. FIFO collects up to 32 values and then stops collecting data, collecting new data only when FIFO is not full. FIFO holds the last 32 data values. When FIFO is full, the oldest data is overwritten with newer data. When triggered by the trigger bit, FIFO holds the last data samples before the trigger event and then continues to collect data until FIFO is full. New data is collected only when FIFO is not full. SPI Bit A value of 1 in the SPI bit sets the device to 3-wire SPI mode, and a value of 0 sets the device to 4-wire SPI mode. INT_INVERT Bit A value of 0 in the INT_INVERT bit sets the interrupts to active high, and a value of 1 sets the interrupts to active low. FULL_RES Bit When this bit is set to a value of 1, the device is in full resolution mode, where the output resolution increases with the g range set by the range bits to maintain a 4 mg/LSB scale factor. When the FULL_RES bit is set to 0, the device is in 10-bit mode, and the range bits determine the maximum g range and scale factor. 1 0 Stream 1 1 Trigger Justify Bit A setting of 1 in the justify bit selects left-justified (MSB) mode, and a setting of 0 selects right-justified mode with sign extension. Trigger Bit A value of 0 in the trigger bit links the trigger event of trigger mode to INT1, and a value of 1 links the trigger event to INT2. Range Bits These bits set the g range as described in Table 21. Table 21. g Range Setting D1 0 0 1 1 Setting D0 0 1 0 1 g Range 2 g 4 g 8 g 16 g Samples Bits The function of these bits depends on the FIFO mode selected (see Table 23). Entering a value of 0 in the samples bits immediately sets the watermark bit in the INT_SOURCE register (Address 0x30), regardless of which FIFO mode is selected. Undesirable operation may occur if a value of 0 is used for the samples bits when trigger mode is used. Table 23. Samples Bits Functions FIFO Mode Bypass FIFO Stream Trigger Samples Bits Function None. Specifies how many FIFO entries are needed to trigger a watermark interrupt. Specifies how many FIFO entries are needed to trigger a watermark interrupt. Specifies how many FIFO samples are retained in the FIFO buffer before a trigger event. Register 0x32 to Register 0x37--DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) These six bytes (Register 0x32 to Register 0x37) are eight bits each and hold the output data for each axis. Register 0x32 and Register 0x33 hold the output data for the x-axis, Register 0x34 and Register 0x35 hold the output data for the y-axis, and Register 0x36 and Register 0x37 hold the output data for the z-axis. The output data is twos complement, with DATAx0 as the least significant byte Rev. 0 | Page 26 of 40 ADXL346 Register 0x39--FIFO_STATUS (Read Only) D7 FIFO_TRIG D6 0 D5 D4 D3 D2 Entries D1 D0 FIFO_TRIG Bit A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring, and a 0 means that a FIFO trigger event has not occurred. An orientation interrupt is generated whenever the orientation status for the mode selected by the INT_3D bit changes in the orient register (Address 0x3C). The orientation interrupt is cleared by reading the INT_SOURCE register. Clearing the INT_ORIENT bit, or the orientation bit in the INT_ENABLE register (Address 0x2E), disables and clears the interrupt. Writing to the BW_RATE register (Address 0x2C) or placing the part into standby mode resets the orientation feature, clearing the orientation filter and the interrupt. However, resetting the orientation feature also resets the orientation status in the orient register (Address 0x3C) and, therefore, causes an interrupt to be generated when the next output sample is available if the present orientation is not the default orientation. A value of 0 for the INT_ORIENT bit disables generation of the orientation interrupt and permits the use of the overrun function. Entries Bits These bits report how many data values are stored in FIFO. Access to collect the data from FIFO is provided through the DATAX, DATAY, and DATAZ registers. FIFO reads must be done in burst or multiple-byte mode because each FIFO level is cleared after any read (single- or multiple-byte) of FIFO. FIFO stores a maximum of 32 entries, which equates to a maximum of 33 entries available at any given time because an additional entry is available at the output filter of the device. Dead Zone Bits These bits determine the region between two adjacent orientations, where the orientation is considered invalid and is not updated. A value of 0 may result in undesirable behavior when the orientation is close to the bisector between two adjacent regions. The dead zone angle is determined by these bits, as described in Table 24. See the Orientation Sensing section for more details. Table 24. Dead Zone and Divisor Codes Decimal 0 1 2 3 4 5 6 7 Binary 000 001 010 011 100 101 110 111 Dead Zone Angle (Degrees) 5.1 10.2 15.2 20.4 25.5 30.8 36.1 41.4 Divisor Bandwidth (Hz) ODR/9 ODR/22 ODR/50 ODR/100 ODR/200 ODR/400 ODR/800 ODR/1600 Register 0x3A--TAP_SIGN (Read Only) D7 0 D6 XSIGN D5 YSIGN D4 ZSIGN D3 0 D2 XTAP D1 YTAP D0 ZTAP xSIGN Bits These bits indicate the sign of the first axis involved in a tap event. A setting of 1 corresponds to acceleration in the negative direction, and a setting of 0 corresponds to acceleration in the positive direction. These bits update only when a new singletap/double-tap event is detected, and only the axes enabled in the TAP_AXES register (Address 0x2A) are updated. The TAP_SIGN register should be read before clearing the interrupt. See the Tap Sign section for more details. xTAP Bits These bits indicate the first axis involved in a tap event. A setting of 1 corresponds to involvement in the event, and a setting of 0 corresponds to no involvement. When new data is available, these bits are not cleared but are overwritten by the new data. The TAP_SIGN register should be read before clearing the interrupt. Disabling an axis from participation clears the corresponding source bit when the next single-tap/double-tap event occurs. INT_3D Bit If the orientation interrupt is enabled, the INT_3D bit determines whether 2D or 3D orientation detection generates an interrupt. A value of 0 generates an interrupt only if the 2D orientation changes from a valid 2D orientation to a different valid 2D orientation. A value of 1 generates an interrupt only if the 3D orientation changes from a valid 3D orientation to a different valid 3D orientation. Register 0x3B--ORIENT_CONF (Read/Write) D7 INT_ ORIENT D6 D5 Dead zone D4 D3 INT_ 3D D2 D1 Divisor D0 INT_ORIENT Bit Setting the INT_ORIENT bit enables the orientation interrupt. A value of 1 overrides the overrun function of the device and replaces overrun in the INT_MAP (Address 0x2F), INT_ENABLE (Address 0x2E), and INT_SOURCE (Address 0x30) registers with the orientation function. After setting the INT_ORIENT bit, the orientation bits in the INT_MAP and INT_ENABLE registers must be configured to map the orientation interrupt to INT1 or INT2 and to enable generation of the interrupt to the pin. Divisor Bits These bits set the bandwidth of the filter used to low-pass filter the measured acceleration for stable orientation sensing. The divisor bandwidth is determined by these bits, as detailed in Table 24, where ODR is the output data rate set in the BW_RATE register (Address 0x2C). See the Orientation Sensing section for more details. Rev. 0 | Page 27 of 40 ADXL346 Register 0x3C--Orient (Read Only) D7 0 D6 V2 D5 D4 2D_ORIENT D3 V3 D2 D1 D0 3D_ORIENT Vx Bits These bits show the validity of the 2D (V2) and 3D (V3) orientations. A value of 1 corresponds to the orientation being valid. A value of 0 means that the orientation is invalid because the current orientation is in the dead zone. Writing to the BW_RATE register (Address 0x2C) or placing the part into standby mode resets the orientation feature, clearing the orientation filter and the orientation status. An orientation interrupt (if enabled) results from these actions if the orientation during the next output sample is different from the default value (+X for 2D orientation detection and undefined for 3D orientation). Table 25. 2D Orientation Codes Decimal 0 1 2 3 Binary 00 01 10 11 Orientation Portrait positive Portrait negative Landscape positive Landscape negative Dominant Axis +X -X +Y -Y xD_ORIENT Bits These bits represent the current 2D (2D_ORIENT) and 3D (3D_ORIENT) orientations of the accelerometer. If the orientation interrupt is enabled, this register is read to determine the orientation of the device when the interrupt occurs. Because this register updates with each new sample of acceleration data, it should be read at the time of the orientation interrupt to ensure that the orientation change that caused the interrupt has been identified. Orientation values are shown in Table 25 and Table 26. See the Orientation Sensing section for more details. Table 26. 3D Orientation Codes Decimal 3 4 2 5 1 6 Binary 011 100 010 101 001 110 Orientation Front Back Left Right Top Bottom Dominant Axis +X -X +Y -Y +Z -Z Rev. 0 | Page 28 of 40 ADXL346 APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING A 1 F tantalum capacitor (CS) at VS and a 0.1 F ceramic capacitor (CI/O) at VDD I/O placed close to the ADXL346 supply pins is recommended to adequately decouple the accelerometer from noise on the power supply. If additional decoupling is necessary, a resistor or ferrite bead, no larger than 100 , in series with VS may be helpful. Additionally, increasing the bypass capacitance on VS to a 10 F tantalum capacitor in parallel with a 0.1 F ceramic capacitor may also improve noise. Care should be taken to ensure that the connection from the ADXL346 ground to the power supply ground has low impedance because noise transmitted through ground has an effect similar to noise transmitted through VS. It is recommended that VS and VDD I/O be separate supplies to minimize digital clock noise on the VS supply. If this is not possible, additional filtering of the supplies as previously mentioned may be necessary. VS CS VS VDD I/O SDA/SDI/SDIO INTERRUPT CONTROL INT1 SDO/ALT ADDRESS SCL/SCLK INT2 GND CS XHI BW THRESHOLD (THRESH_TAP) TAP DETECTION The tap interrupt function is capable of detecting either single or double taps. The following parameters are shown in Figure 45 for a valid single-tap event and a valid double-tap event: * * * The tap detection threshold is defined by the THRESH_TAP register (Address 0x1D). The maximum tap duration time is defined by the DUR register (Address 0x21). The tap latency time is defined by the latent register (Address 0x22) and is the waiting period from the end of the first tap until the start of the time window when a second tap can be detected, which is determined by the value in the window register (Address 0x23). The interval after the latency time (set by the latent register) is defined by the window register. Although a second tap must begin after the latency time has expired, it need not finish before the end of the time defined by the window register. FIRST TAP SECOND TAP * VDD I/O CI/O ADXL346 3-WIRE OR 4-WIRE SPI OR I2C INTERFACE 08167-035 TIME LIMIT FOR TAPS (DUR) LATENCY TIME (LATENT) TIME WINDOW FOR SECOND TAP (WINDOW) Figure 43. Applications Diagram INTERRUPTS MECHANICAL CONSIDERATIONS FOR MOUNTING The ADXL346 should be mounted on the PCB in a location close to a hard mounting point of the PCB to the case. Mounting the ADXL346 at an unsupported PCB location, as shown in Figure 44, may result in large, apparent measurement errors due to undampened PCB vibration. Locating the accelerometer near a hard mounting point ensures that any PCB vibration at the accelerometer is above the accelerometer's mechanical sensor resonant frequency and, therefore, effectively invisible to the accelerometer. Multiple mounting points, close to the sensor, and/or a thicker PCB also help to reduce the effect of system resonance on the performance of the sensor. ACCELEROMETERS PCB Figure 45. Tap Interrupt Function with Valid Single and Double Taps If only the single-tap function is in use, the single-tap interrupt is triggered when the acceleration goes below the threshold, as long as DUR has not been exceeded. If both single and doubletap functions are in use, the single-tap interrupt is triggered when the double-tap event has been either validated or invalidated. Several events can occur to invalidate the second tap of a double-tap event. First, if the suppress bit in the TAP_AXES register (Address 0x2A) is set, any acceleration spike above the threshold during the latency time (set by the latent register) invalidates the double-tap detection, as shown in Figure 46. MOUNTING POINTS Figure 44. Incorrectly Placed Accelerometers 08167-036 Rev. 0 | Page 29 of 40 08167-037 SINGLE-TAP INTERRUPT DOUBLE-TAP INTERRUPT ADXL346 INVALIDATES DOUBLE TAP IF SUPRESS BIT IS SET TIME LIMIT FOR TAPS (DUR) LATENCY TIME (LATENT) TIME WINDOW FOR SECOND TAP (WINDOW) 08167-038 DUR, latent, window, and THRESH_TAP registers is required. In general, a good starting point is to set the DUR register to a value greater than 0x10 (10 ms), the latent register to a value greater than 0x10 (20 ms), the window register to a value greater than 0x40 (80 ms), and the THRESH_TAP register to a value greater than 0x30 (3 g). Setting a very low value in the latent, window, or THRESH_TAP register may result in an unpredictable response due to the accelerometer picking up echoes of the tap inputs. After a tap interrupt has been received, the first axis to exceed the THRESH_TAP level is reported in the ACT_TAP_STATUS register (Address 0x2B). This register is never cleared but is overwritten with new data. XHI BW Figure 46. Double-Tap Event Invalid Due to High g Event When the Suppress Bit Is Set A double-tap event can also be invalidated if acceleration above the threshold is detected at the start of the time window for the second tap (set by the window register (Address 0x23)). This results in an invalid double tap at the start of this window, as shown in Figure 47. Additionally, a double-tap event can be invalidated if an acceleration exceeds the time limit for taps (set by the DUR register (Address 0x21)), resulting in an invalid double tap at the end of the DUR time limit for the second tap event, also shown in Figure 47. INVALIDATES DOUBLE TAP AT START OF WINDOW IMPROVED TAP DETECTION Improved tap detection is enabled by setting the improved tap bit of the TAP_AXES register (Address 0x2A). When improved tap detection is enabled, the filtered output data corresponding to the output data rate set in the BW_RATE register (Address 0x2C) is processed to determine if a tap event occurred. In addition, an ac-coupled differential measurement is used. This results in the timing values and threshold values for improved tap detection being different from those used for normal tap detection. When improved tap detection is used, new values must be determined based on test results. In general, no timing values (in the DUR, latent, or window registers) should be set that are less than the time step resolution set by the output data rate. The threshold value for improved tap detection can typically be set much lower than the threshold for normal tap detection. The value used depends on the value in the BW_RATE register and should be determined through system testing. Refer to the Threshold section for more details. XHI BW TIME LIMIT FOR TAPS (DUR) TIME LIMIT FOR TAPS (DUR) LATENCY TIME (LATENT) TIME WINDOW FOR SECOND TAP (WINDOW) TIME LIMIT FOR TAPS (DUR) TAP SIGN A negative sign is produced by experiencing a negative acceleration, which corresponds to tapping on the positive face of the device for the desired axis. The positive face of the device is the face such that movement in that direction is positive acceleration. For example, tapping on the face that corresponds to the +X direction, labeled as front in Figure 48, results in a negative sign for the x-axis. Tapping on the face labeled as left in Figure 48 results in a negative sign for the y-axis, and tapping on the face labeled top results in a negative sign for the z-axis. Conversely, tapping on the back, right, or bottom sides results in positive signs for the corresponding axes. +z TOP (+Z) +y LEFT (+Y) +x FRONT (+X) 08167-046 XHI BW Figure 47. Tap Interrupt Function with Invalid Double Taps Single taps, double taps, or both can be detected by setting the respective bits in the INT_ENABLE register (Address 0x2E). Control over participation of each of the three axes in single-tap/ double-tap detection is exerted by setting the appropriate bits in the TAP_AXES register (Address 0x2A). For the double-tap function to operate, both the latent and window registers must be set to a nonzero value. Every mechanical system has somewhat different single-tap/ double-tap responses based on the mechanical characteristics of the system. Therefore, some experimentation with values for the 08167-039 INVALIDATES DOUBLE TAP AT END OF DUR Figure 48. 3D Orientation with Coordinate System Rev. 0 | Page 30 of 40 ADXL346 THRESHOLD The lower output data rates are achieved by decimating a common sampling frequency inside the device. The activity, free-fall, and single-tap/double-tap detection functions without improved tap enabled are performed using undecimated data. As the bandwidth of the output data varies with the data rate and is lower than the bandwidth of the undecimated data, the high frequency and high g data that is used to determine activity, free-fall, and single-tap/double-tap events may not be present if the output of the accelerometer is examined. This may result in functions triggering when acceleration data does not appear to meet the conditions set by the user for the corresponding function. and application of any compounds on or over the component. If calibration is deemed necessary, it is recommended that calibration be performed after system assembly to compensate for these effects. A simple method of calibration is to measure the offset while assuming that the sensitivity of the ADXL346 is as specified in Table 1. The offset can then be automatically accounted for by using the built-in offset registers (Register 0x1E, Register 0x1F, and Register 0x20). This results in the data acquired from the DATAX, DATAY, and DATAZ registers (Address 0x32 to Address 0x37) already compensating for any offset. In a no-turn or single-point calibration scheme, the part is oriented such that one axis, typically the z-axis, is in the 1 g field of gravity and the remaining axes, typically the x- and y-axes, are in a 0 g field. The output is then measured by taking the average of a series of samples. The number of samples averaged is a choice of the system designer, but a recommended starting point is 0.1 sec worth of data for data rates of 100 Hz or greater. This corresponds to 10 samples at the 100 Hz data rate. For data rates of less than 100 Hz, it is recommended that at least 10 samples be averaged together. These values are stored as X0g, Y0g, and Z+1g for the 0 g measurements on the x- and y-axes and the 1 g measurement on the z-axis, respectively. The values measured for X0g and Y0g correspond to the offset of the x- and y-axes, and compensation is done by subtracting those values from the output of the accelerometer to obtain the actual acceleration: XACTUAL = XMEAS - X0g YACTUAL = YMEAS - Y0g Because the z-axis measurement is done in a 1 g field, a no-turn or single-point calibration scheme assumes an ideal sensitivity, SZ, for the z-axis. This is subtracted from Z+1g to attain the z-axis offset, which is then subtracted from future measured values to obtain the actual value: Z0g = Z1g - SZ ZACTUAL = ZMEAS - Z0g The ADXL346 can automatically compensate the output for offset by using the offset registers (Register 0x1E, Register 0x1F, and Register 0x20). These registers contain an 8-bit, twos complement value that is automatically added to all measured acceleration values, and the result is then placed into the DATAX, DATAY, and DATAZ registers. Because the value placed in an offset register is additive, a negative value is placed into the register to eliminate a positive offset and vice versa for a negative offset. The register has a scale factor of 15.6 mg/LSB and is independent of the selected g range. As an example, assume that the ADXL346 is placed into fullresolution mode with a sensitivity of typically 256 LSB/g. The part is oriented such that the z-axis is in the field of gravity and the outputs of the x-, y-, and z-axes are measured as +10 LSB, -13 LSB, and +9 LSB, respectively. Using the previous equations, X0g is +10 LSB, Y0g is -13 LSB, and Z0g is +9 LSB. Each LSB of LINK MODE The function of the link bit is to reduce the number of activity interrupts that the processor must service by setting the device to look for activity only after inactivity. For proper operation of this feature, the processor must still respond to the activity and inactivity interrupts by reading the INT_SOURCE register (Address 0x30) and, therefore, clearing the interrupts. If an activity interrupt is not cleared, the part cannot go into autosleep mode. The asleep bit in the ACT_TAP_STATUS register (Address 0x2B) indicates whether the part is asleep. SLEEP MODE VS. LOW POWER MODE In applications where a low data rate and low power consumption are desired (at the expense of noise performance), it is recommended that low power mode be used. The use of low power mode preserves the functionality of the DATA_READY interrupt and the FIFO for postprocessing of the acceleration data. Sleep mode, while offering a low data rate and power consumption, is not intended for data acquisition. However, when sleep mode is used in conjunction with the AUTO_SLEEP mode and the link mode, the part can automatically switch to a low power, low sampling rate mode when inactivity is detected. To prevent the generation of redundant inactivity interrupts, the inactivity interrupt is automatically disabled and activity is enabled. When the ADXL346 is in sleep mode, the host processor can also be placed into sleep mode or low power mode to save significant system power. Once activity is detected, the accelerometer automatically switches back to the original data rate of the application and provides an activity interrupt that can be used to wake up the host processor. Similar to when inactivity occurs, detection of activity events is disabled and inactivity is enabled. OFFSET CALIBRATION Accelerometers are mechanical structures containing elements that are free to move. These moving parts can be very sensitive to mechanical stresses, much more so than solid-state electronics. The 0 g bias or offset is an important accelerometer metric because it defines the baseline for measuring acceleration. Additional stresses can be applied during assembly of a system containing an accelerometer. These stresses can come from, but are not limited to, component soldering, board stress during mounting, Rev. 0 | Page 31 of 40 ADXL346 output in full-resolution is 3.9 mg or one-quarter of an LSB of the offset register. Because the offset register is additive, the 0 g values are negated and rounded to the nearest LSB of the offset register: XOFFSET = -Round(10/4) = -3 LSB YOFFSET = -Round(-13/4) = 3 LSB ZOFFSET = -Round(9/4) = -2 LSB These values are programmed into the OFSX, OFSY, and OFXZ registers, respectively, as 0xFD, 0x03, and 0xFE. As with all registers in the ADXL346, the offset registers do not retain the value written into them when power is removed from the part. Power-cycling the ADXL346 returns the offset registers to their default value of 0x00. Because the no-turn or single-point calibration method assumes an ideal sensitivity in the z-axis, any error in the sensitivity results in offset error. For instance, if the actual sensitivity was 250 LSB/g in the previous example, the offset would be 15 LSB, not 9 LSB. To help minimize this error, an additional measurement point can be used with the z-axis in a 0 g field, and the 0 g measurement can be used in the ZACTUAL equation. recommended that at least 10 samples be averaged together. The averaged values should be stored and labeled appropriately as the self-test disabled data, that is, XST_OFF, YST_OFF, and ZST_OFF. Next, self-test should be enabled by setting Bit D7 of the DATA_FORMAT register (Address 0x31). The output needs some time (about four samples) to settle once self-test is enabled. After allowing the output to settle, several samples of acceleration data for the x-, y-, and z-axes should be taken again and averaged. It is recommended that the same number of samples be taken for this average as was previously taken. These averaged values should again be stored and labeled appropriately as the value with selftest enabled, that is, XST_ON, YST_ON, and ZST_ON. Self-test can then be disabled by clearing Bit D7 of the DATA_FORMAT register (Address 0x31). With the stored values for self-test enabled and disabled, the self-test change is as follows: XST = XST_ON - XST_OFF YST = YST_ON - YST_OFF ZST = ZST_ON - ZST_OFF Because the measured output for each axis is expressed in LSBs, XST, YST, and ZST are also expressed in LSBs. These values can be converted to g's of acceleration by multiplying each value by the 3.9 mg/LSB scale factor, if configured for full-resolution mode. Additionally, Table 15 through Table 18 correspond to the self-test range converted to LSBs and can be compared with the measured self-test change when operating at a VS of 2.6 V. For other voltages, the minimum and maximum self-test output values should be adjusted based on (multiplied by) the scale factors shown in Table 14. If the part was placed into 2 g, 10-bit or full-resolution mode, the values listed in Table 15 should be used. Although the fixed 10-bit mode or a range other than 16 g can be used, a different set of values, as indicated in Table 16 through Table 18, would need to be used. Using a range below 8 g may result in insufficient dynamic range and should be considered when selecting the range of operation for measuring self-test. If the self-test change is within the valid range, the test is considered successful. Generally, a part is considered to pass if the minimum magnitude of change is achieved. However, a part that changes by more than the maximum magnitude is not necessarily a failure. USING SELF-TEST The self-test change is defined as the difference between the acceleration output of an axis with self-test enabled and the acceleration output of the same axis with self-test disabled (see Endnote 7 of Table 1). This definition assumes that the sensor does not move between these two measurements, because if the sensor moves, a non-self-test related shift corrupts the test. Proper configuration of the ADXL346 is also necessary for an accurate self-test measurement. The part should be set with a data rate greater than or equal to 100 Hz. This is done by ensuring that a value greater than or equal to 0x0A is written into the rate bits (Bit D3 through Bit D0) in the BW_RATE register (Address 0x2C). The part also must be placed into normal power operation by ensuring that the LOW_POWER bit (Bit D4) in the BW_RATE register is cleared (LOW_POWER bit = 0) for accurate self-test measurements. It is recommended that the part be set to fullresolution, 16 g mode to ensure that there is sufficient dynamic range for the entire self-test shift. This is done by setting the FULL_RES bit (Bit D3) and writing a value of 0x03 to the range bits (Bit D1 and Bit D0) of the DATA_FORMAT register (Address 0x31). This results in a high dynamic range for measurement and a 3.9 mg/LSB scale factor. After the part is configured for accurate self-test measurement, several samples of acceleration data for the x-, y-, and z-axes should be retrieved from the sensor and averaged together. The number of samples averaged is a choice of the system designer, but a recommended starting point is 0.1 sec worth of data for data rates of 100 Hz or greater. This corresponds to 10 samples at the 100 Hz data rate. For data rates of less than 100 Hz, it is ORIENTATION SENSING The orientation function of the ADXL346 reports both 2D and 3D orientation concurrently through the orient register (Address 0x3C). The V2 and V3 bits (Bit D6 and Bit D3 in the orient register) report the validity of the 2D and 3D orientation codes. If V2 or V3 are set, their respective code is a valid orientation. If V2 or V3 are cleared, the orientation of the accelerometer is unknown, such as when the orientation is within the dead zone between valid regions. Rev. 0 | Page 32 of 40 ADXL346 For 2D orientation sensing, the relation of the x- and y-axes to gravity is used to determine the accelerometer orientation (see Figure 49 and Table 25). Portrait positive corresponds to the x-axis being most closely aligned to the gravity vector and directed upwards, opposite the gravity vector. Portrait negative is the opposite of portrait positive, with the x-axis pointing downwards along the gravity vector. Landscape positive corresponds to the y-axis being most closely aligned with the gravity vector and directed upwards, away from the gravity vector. Landscape negative is the orientation opposite landscape positive. The dead zone regions are shown in the orientations for portrait positive (+X) and portrait negative (-X) of Figure 49. These regions also exist for landscape positive (+Y) and landscape negative (-Y), as shown in Figure 49. In 3D orientation, the z-axis is also included. If the accelerometer is placed in a Cartesian coordinate system, as shown in Figure 48 of the Tap Sign section, the top of the device corresponds to the positive z-axis direction, the front of the device corresponds to the positive x-axis direction, and the right side of the device corresponds to the positive y-axis direction. The states shown in Table 26 correspond to which side of the accelerometer is directed upwards, opposite the gravity vector. As shown in Figure 48, the accelerometer is oriented in the top state. If the device is flipped over such that the top of the device is facing down, toward gravity, the orientation is reported as the bottom state. If the device is adjusted such that the positive x-axis or positive y-axis direction is pointing upwards, away from the gravity vector, the accelerometer reports the orientation as front or left, respectively. The algorithm to detect orientation change is performed after filtering the output acceleration data to eliminate the effects of high frequency motion. This is performed by using a low-pass filter with a bandwidth set by the divisor bits (ORIENT_CONF register, Address 0x3B). The orientation filter uses the same output data available in the output data registers (Address 0x32 to Address 0x37); therefore, the orient register (Address 0x3C) is updated at the same rate as the data rate that is set in the BW_RATE register (Address 0x2C). Because the output data is used, the bandwidth of the orientation filter depends on the value set in the BW_RATE register, and the divisor bandwidth values in Table 24 are referenced to the selected output data rate. To eliminate most human motion, such as walking or shaking, the value in the divisor bits (Bits[D2:D0]) of the ORIENT_CONF register (Address 0x3B) should be selected to effectively limit the orientation bandwidth to 1 Hz or 2 Hz. For example, with an output data rate of 100 Hz, a divisor selection of 3 (ODR/100) results in a 1 Hz bandwidth for orientation detection. For best results, it is recommended that an output data rate of 25 Hz in normal power mode and 200 Hz in low power operation be used. PORTRAIT POSITIVE (00) +X NEGATIVE (01) DEADZONES +Y +g +g +Y +X LANDSCAPE POSITIVE (10) +Y NEGATIVE (11) +g +X +X +g +Y Figure 49. 2D Orientation with Corresponding Codes The width of the dead zone region between two orientation positions is determined by setting the value of the dead zone bits (Bits[D6:D4]) in the ORIENT_CONF register (Address 0x3B). The dead zone region size can be specified as per the values shown in Table 24. The dead zone angle represents the total angle where the orientation is considered invalid. Therefore, a dead zone of 15.4 corresponds to 7.7 in either direction away from the bisector of two bordering regions. An example with a dead zone region of 15.4 is shown in Figure 50. It should be noted that the values shown in Table 24 correspond to the typical dead zone angle when the gravity vector is completely contained in only two axes (xy, xz, or yz) and should be used only as a starting point. If the device is oriented such that the projection of gravity onto all three axes is nonzero, the effective sensitivity is reduced, causing an increase in the dead zone angle. Therefore, evaluation needs to be performed for specific application uses to determine the optimal setting for the dead zone. PORTRAIT POSITIVE 52.7 45 37.3 LANDSCAPE POSITIVE +Y 08167-041 DEADZONE +X +g Figure 50. Orientation Showing a 15.4 Dead Zone Region By setting the INT_ORIENT bit (Bit D7) of the ORIENT_CONF register (Address 0x3B), an interrupt can be generated when the device is placed into a new valid orientation. Only one mode of orientation detection, 2D or 3D, can generate an interrupt at a time. The orientation detection mode is selected by setting or clearing the INT_3D bit (Bit D3) of the ORIENT_CONF register (Address 0x3B). For more details, refer to the Register 0x3B-- ORIENT_CONF (Read/Write) section. Rev. 0 | Page 33 of 40 08167-040 ADXL346 Writing to the BW_RATE register or placing the part into standby mode resets the orientation feature, clearing the orientation filter and the orientation status. These actions cause an orientation interrupt (if enabled), however, if the orientation during the next output sample is different from the default value (+X for 2D orientation detection and undefined for 3D orientation). the LSB of the output data-word is Bit D6 of the DATAx0 register. In full-resolution operation when data is left justified, the location of the LSB changes according to the selected output range. For a range of 2 g, the LSB is Bit D6 of the DATAx0 register; for 4 g, Bit D5 of the DATAx0 register; for 8 g, Bit D4 of the DATAx0 register; and for 16 g, Bit D3 of the DATAx0 register. This is shown in Figure 52. The use of 3200 Hz and 1600 Hz output data rates for fixed 10-bit operation in the 4 g, 8 g, and 16 g output ranges provides an LSB that is valid and that changes according to the applied acceleration. Therefore, in these modes of operation, Bit D0 is not always 0 when output data is right justified, and Bit D6 is not always 0 when output data is left justified. Operation at any data rate of 800 Hz or lower also provides a valid LSB in all ranges and modes that change according to the applied acceleration. DATA FORMATTING OF UPPER DATA RATES Formatting of output data at the 3200 Hz and 1600 Hz output data rates changes depending on the mode of operation (fullresolution or fixed 10-bit) and the selected output range. When using the 3200 Hz or 1600 Hz output data rates in full-resolution or 2 g, 10-bit operation, the LSB of the output data-word is always 0. When data is right justified, this corresponds to Bit D0 of the DATAx0 register, as shown in Figure 51. When data is left justified and the part is operating in 2 g, 10-bit mode, DATAx1 REGISTER DATAx0 REGISTER D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 0 OUTPUT DATA-WORD FOR 16g, FULL-RESOLUTION MODE. OUTPUT DATA-WORD FOR THE 2g, FULL-RESOLUTION AND ALL 10-BIT MODES. Figure 51. Data Formatting When Output Data Is Right Justified DATAx1 REGISTER DATAx0 REGISTER D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 0 MSB FOR ALL MODES OF OPERATION WHEN LEFT JUSTIFIED. LSB FOR 2g, FULL-RESOLUTION AND ALL 10-BIT MODES. LSB FOR 4g, FULL-RESOLUTION MODE. LSB FOR 8g, FULL-RESOLUTION MODE. LSB FOR 16g, FULL-RESOLUTION MODE. 08167-146 FOR 3200Hz AND 1600Hz OUTPUT DATA RATES, THE LSB IN THESE MODES IS ALWAYS 0. ADDITIONALLY, ANY BITS TO THE RIGHT OF THE LSB ARE ALWAYS 0 WHEN THE OUTPUT DATA IS LEFT JUSTIFIED. Figure 52. Data Formatting When Output Data Is Left Justified Rev. 0 | Page 34 of 40 08167-145 THE 4g AND 8g FULL-RESOLUTION MODES HAVE THE SAME LSB LOCATION AS THE 2g AND 16g FULL-RESOLUTION MODES, BUT THE MSB LOCATION CHANGES TO BIT D2 AND BIT D3 OF THE DATAx1 REGISTER FOR 4g AND 8g, RESPECTIVELY. ADXL346 NOISE PERFORMANCE The specification of noise shown in Table 1 corresponds to the typical noise performance of the ADXL346 in normal power operation with an output data rate of 100 Hz (LOW_POWER bit = 0, rate = 0x0A in the BW_RATE register, Address 0x2C). For normal power operation at data rates below 100 Hz, the noise of the ADXL346 is equivalent to the noise at 100 Hz ODR in LSBs. For data rates greater than 100 Hz, the noise increases approximately by a factor of 2 per doubling of the data rate. For example, at 400 Hz ODR, the noise on the x- and y-axes is typically less than 2 LSB rms, and the noise on the z-axis is typically less than 3 LSB rms. For low power operation (LOW_POWER bit = 1 in the BW_RATE register, Address 0x2C), the noise of the ADXL346 is constant for all valid data rates shown in Table 8. This value is typically less than 2.83 LSB rms for the x- and y-axes and typically less than 4.25 LSB rms for the z-axis. The trend of noise performance for both normal power and low power modes of operation of the ADXL346 is shown in Figure 53. Figure 54 shows the typical Allan deviation for the ADXL346. The 1/f corner of the device, as shown in this figure, is very low, allowing absolute resolution of approximately 100 g (assuming that there is sufficient integration time). The figure also shows that the noise density is 420 g/Hz for the x- and y-axes and 530 g/Hz for the z-axis. Figure 55 shows the typical noise performance trend of the ADXL346 over supply voltage. The performance is normalized to the tested and specified supply voltage, VS = 2.6 V. The x-axis offers the best noise performance over supply voltage, increasing by typically less than 25% from nominal at a supply voltage of 1.8 V. The performance of the y- and z-axes is comparable, with both axes increasing by typically less than 35% when operating with a supply voltage of 1.8 V. It should be noted, as shown in Figure 53, that the noise on the z-axis is typically higher than that on the y-axis; therefore, although the noise on the z- and y-axes change roughly the same in percentage over supply voltage, the magnitude of change on the z-axis is greater than the magnitude of change on the y-axis. 7 X-AXIS, NORMAL POWER Y-AXIS, NORMAL POWER Z-AXIS, NORMAL POWER X-AXIS, LOW POWER Y-AXIS, LOW POWER Z-AXIS, LOW POWER 10k X-AXIS Y-AXIS Z-AXIS ALLAN DEVIATION (g) 1k 100 10 0.01 0.1 1 10 100 AVERAGING PERIOD, (s) 1k 10k Figure 54. Allan Deviation 150 PERCENTAGE OF NORMALIZED NOISE (%) X-AXIS 140 Y-AXIS Z-AXIS 130 120 110 100 08167-149 90 1.6 1.8 2.0 2.2 2.4 2.6 SUPPLY VOLTAGE, VS (V) 2.8 Figure 55. Normalized Noise vs. Supply Voltage OPERATION AT VOLTAGES OTHER THAN 2.6 V The ADXL346 is tested and specified at a supply voltage of VS = 2.6 V; however, it can be powered with a VS as high as 2.75 V or as low as 1.7 V. Some performance parameters change as the supply voltage changes, including the offset, sensitivity, noise, self-test, and supply current. Due to minuscule changes in the electrostatic forces as supply voltage is varied, the offset and sensitivity change slightly. When operating at a supply voltage of VS = 1.8 V, the offset of the x- and y-axes is typically 25 mg higher than at VS = 2.6 V operation. The z-axis is typically 20 mg lower when operating at a supply voltage of 1.8 V than when operating at VS = 2.6 V. Sensitivity on the x- and y-axes typically shifts from a nominal 256 LSB/g (fullresolution or 2 g, 10-bit operation) at VS = 2.6 V operation to 250 LSB/g when operating with a supply voltage of 1.8 V. The z-axis sensitivity is unaffected by a change in supply voltage and is the same at VS = 1.8 V operation as it is at VS = 2.6 V operation. Simple linear interpolation can be used to determine typical shifts in offset and sensitivity at other supply voltages. 6 OUTPUT NOISE (LSB rms) 5 4 3 2 0 3.13 6.25 12.50 25 50 100 200 400 OUTPUT DATA RATE (Hz) 800 1600 3200 Figure 53. Noise vs. Output Data Rate for Normal and Low Power Modes, Full Resolution (256 LSB/g) Rev. 0 | Page 35 of 40 08167-147 1 08167-148 ADXL346 Changes in noise performance, self-test response, and supply current are discussed elsewhere throughout the data sheet. For more information about noise performance, review the Noise Performance section. The Self-Test section discusses both the operation of self-test over voltage (a square relationship with the supply voltage) and the conversion of the self-test response in g's to LSBs. Finally, Figure 33 shows the impact of supply voltage on typical current consumption at a 100 Hz output data rate, with all other output data rates following the same trend. 140 120 NORMALIZED OUTPUT (LSB) 100 80 60 0.10Hz 0.20Hz 0.39Hz 0.78Hz 1.56Hz 3.13Hz 6.25Hz 08167-056 40 20 OFFSET PERFORMANCE AT LOWEST DATA RATES The ADXL346 offers several output data rates and bandwidths designed for a wide range of applications. However, at the lowest data rates, described as those data rates below 6.25 Hz, the offset performance over temperature can vary significantly from the remaining data rates. Figure 56, Figure 57, and Figure 58 show the typical offset performance of the ADXL346 over temperature for data rates of 6.25 Hz and lower. All plots are normalized to the offset at 100 Hz output data rate; therefore, a nonzero value corresponds to additional offset shift due to the temperature for that data rate. When using the lowest data rates, it is recommended that the operating temperature range of the device be limited to provide minimal offset shift across the operating temperature range. Due to variability between parts, it is also recommended that calibration over temperature be performed if any data rates below 6.25 Hz are in use. 0 25 35 45 55 65 75 85 TEMPERATURE (C) Figure 56. Typical X-Axis Output vs. Temperature at Lower Data Rates, Normalized to 100 Hz Output Data Rate, VS = 2.6 V 140 120 NORMALIZED OUTPUT (LSB) 100 80 60 0.10Hz 0.20Hz 0.39Hz 0.78Hz 1.56Hz 3.13Hz 6.25Hz 08167-057 40 20 0 25 35 45 55 65 75 85 TEMPERATURE (C) Figure 57. Typical Y-Axis Output vs. Temperature at Lower Data Rates, Normalized to 100 Hz Output Data Rate, VS = 2.6 V 140 120 NORMALIZED OUTPUT (LSB) 100 80 60 40 20 0 -20 25 35 45 55 65 75 85 TEMPERATURE (C) 0.10Hz 0.20Hz 0.39Hz 0.78Hz 1.56Hz 3.13Hz 6.25Hz 08167-058 Figure 58. Typical Z-Axis Output vs. Temperature at Lower Data Rates, Normalized to 100 Hz Output Data Rate, VS = 2.6 V Rev. 0 | Page 36 of 40 ADXL346 AXES OF ACCELERATION SENSITIVITY AZ AY AX Figure 59. Axes of Acceleration Sensitivity (Corresponding Output Increases When Accelerated Along the Sensitive Axis) XOUT = +1g YOUT = 0g ZOUT = 0g TOP GRAVITY XOUT = 0g YOUT = -1g ZOUT = 0g XOUT = 0g YOUT = +1g ZOUT = 0g TOP XOUT = -1g YOUT = 0g ZOUT = 0g Figure 60. Output Response vs. Orientation to Gravity Rev. 0 | Page 37 of 40 08167-043 XOUT = 0g YOUT = 0g ZOUT = +1g 08167-042 TOP TOP XOUT = 0g YOUT = 0g ZOUT = -1g ADXL346 LAYOUT AND DESIGN RECOMMENDATIONS Figure 61 shows the recommended printed wiring board land pattern. Figure 62 and Table 27 provide details about the recommended soldering profile. 0.8000 0.3000 3.3500 0.5000 3.3500 08167-044 Figure 61. Recommended Printed Wiring Board Land Pattern (Dimensions shown in millimeters) TP RAMP-UP tP CRITICAL ZONE TL TO TP TEMPERATURE TL TSMAX TSMIN tL tS PREHEAT RAMP-DOWN t25C TO PEAK TIME Figure 62. Recommended Soldering Profile Table 27. Recommended Soldering Profile 1, 2 Profile Feature Average Ramp Rate from Liquid Temperature (TL) to Peak Temperature (TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time from TSMIN to TSMAX (tS) TSMAX to TL Ramp-Up Rate Liquid Temperature (TL) Time Maintained Above TL (tL) Peak Temperature (TP) Time of Actual TP - 5C (tP) Ramp-Down Rate Time 25C to Peak Temperature 1 2 08167-045 Sn63/Pb37 3C/sec max 100C 150C 60 sec to 120 sec 3C/sec max 183C 60 sec to 150 sec 240 + 0/-5C 10 sec to 30 sec 6C/sec max 6 minutes max Condition Pb-Free 3C/sec max 150C 200C 60 sec to 180 sec 3C/sec max 217C 60 sec to 150 sec 260 + 0/-5C 20 sec to 40 sec 6C/sec max 8 minutes max Based on JEDEC Standard J-STD-020D.1. For best results, the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used. Rev. 0 | Page 38 of 40 ADXL346 OUTLINE DIMENSIONS PIN 1 CORNER 3.10 3.00 SQ 2.90 0.10 0.50 BSC 13 14 16 1 0.350 0.250 0.50 9 8 6 5 TOP VIEW 0.275 1.00 0.95 0.85 END VIEW 0.79 0.74 0.69 BOTTOM VIEW SEATING PLANE Figure 63. 16-Terminal Land Grid Array [LGA] (CC-16-3) Solder Terminations Finish Is Au over Ni Dimensions shown in millimeters ORDERING GUIDE Model 1 ADXL346ACCZ ADXL346ACCZ-RL ADXL346ACCZ-RL7 EVAL-ADXL346Z EVAL-ADXL346Z-M EVAL-ADXL346Z-S 1 Measurement Range (g) 2, 4, 8, 16 2, 4, 8, 16 2, 4, 8, 16 Specified Voltage (V) 2.6 2.6 2.6 Temperature Range -40C to +85C -40C to +85C -40C to +85C 01-13-2010-B Package Description 16-Terminal Land Grid Array [LGA] 16-Terminal Land Grid Array [LGA] 16-Terminal Land Grid Array [LGA] Evaluation Board Analog Devices Inertial Sensor Evaluation System, Includes ADXL346 Satellite ADXL346 Satellite, Standalone Package Option CC-16-3 CC-16-3 CC-16-3 Branding Code Y2Z Y2Z Y2Z Z = RoHS Compliant Part. Rev. 0 | Page 39 of 40 ADXL346 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). Analog Devices offers specific products designated for automotive applications; please consult your local Analog Devices sales representative for details. Standard products sold by Analog Devices are not designed, intended, or approved for use in life support, implantable medical devices, transportation, nuclear, safety, or other equipment where malfunction of the product can reasonably be expected to result in personal injury, death, severe property damage, or severe environmental harm. Buyer uses or sells standard products for use in the above critical applications at Buyer's own risk and Buyer agrees to defend, indemnify, and hold harmless Analog Devices from any and all damages, claims, suits, or expenses resulting from such unintended use. (c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08167-0-5/10(0) Rev. 0 | Page 40 of 40 |
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